sanchayanmaity/gem5
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Since the delayed write stuff is gone, get rid of regWrite

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and merge it with writeBar0

--HG--
extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb
This commit is contained in:
Nathan Binkert 2006-02-25 22:01:05 -05:00
parent 4d01be373e
commit 25b39da69d
2 changed files with 9 additions and 21 deletions
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29
dev/sinic.cc
View file

@ -489,30 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
//uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr,
req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
regWrite(daddr, cpu, data);
return NoFault;
}
void
Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
{
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
VirtualReg &vnic = virtualRegs[index];
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
switch (raddr) {
case Regs::Config:
changeConfig(reg32);
@ -559,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
}
break;
}
return NoFault;
}
void

1
dev/sinic.hh
View file

@ -280,7 +280,6 @@ class Device : public Base
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
/**