Commit graph

9517 commits

Author SHA1 Message Date
Andreas Hansson
754a9570f2 Timing CPU: Remove a redundant port pointer
This patch is trivial and merely prunes a pointer that was never set
or used.
2012-06-08 12:45:24 -04:00
Andreas Hansson
a118c01716 Power: Fix MaxMiscDestRegs which was set to zero
This patch fixes a failing compilation caused by MaxMiscDestRegs being
zero. According to gcc 4.6, the result is a comparison that is always
false due to limited range of data type.
2012-06-08 12:44:17 -04:00
Nilay Vaish
d6609793d4 X86 TLB: Add a missing = sign 2012-06-07 17:03:45 -05:00
Ali Saidi
c80cd4136e mem: Delay deleting of incoming packets by one call.
This patch is a temporary fix until Andreas' four-phase patches
get reviewed and committed. Removing FastAlloc seems to have exposed
an issue which previously was reasonable rare in which packets are freed
before the sending cache is done with them. This change puts incoming packets
no a pendingDelete queue which are deleted at the start of the next call and
thus breaks the dependency between when the caller returns true and when the
packet is actually used by the sending cache.

Running valgrind on a multi-core linux boot and the memtester results in no
valgrind warnings.
2012-06-07 10:59:03 -04:00
Jayneel Gandhi
7183c3fd56 X86 TLB: Fix for gcc 4.4.3
Due to recent changes to X86 TLB, gem5 stopped compiling on
gcc version 4.4.3. This patch provides the fix for that problem. The patch
is tested on gcc 4.4.3. The change is not required for more recent
versions of gcc (like on 4.6.3).
2012-06-07 08:11:00 -05:00
Nilay Vaish
abb85a68f4 Config: call to setWorkCountOptions() for all ISAs 2012-06-07 08:05:31 -05:00
Nilay Vaish
51c23e601e Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
2012-06-07 08:05:30 -05:00
Nilay Vaish
78a72d6972 Config: changes to a couple of error msgs 2012-06-07 08:05:30 -05:00
Anthony Gutierrez
d6da3ff317 cpu: Don't init simple and inorder CPUs if they are defered.
initCPU() will be called to initialize switched out CPUs for the simple and
inorder CPU models. this patch prevents those CPUs from being initialized
because they should get their state from the active CPU when it is switched
out.
2012-06-05 14:20:13 -04:00
Ali Saidi
20d25b9da7 ISA: Back-out NoopMachInst as a StaticInstPtr change. 2012-06-05 13:52:30 -04:00
Ali Saidi
c06970b673 cpt: update some comments in the checkpoint migration script 2012-06-05 10:36:59 -04:00
Ali Saidi
c49e739352 all: Update stats for memory per master and total fix. 2012-06-05 01:23:16 -04:00
William Wang
e5f0d6016b stats: when applying an operation to two vectors sum the components first.
Previously writing X/Y in a formula would result in:
x[0]/y[0] + x[1]/y[1]
In reality you want:
(x[0] +x[1])/(y[0] + y[1])
2012-06-05 01:23:11 -04:00
Dam Sunwoo
14539ccae1 Mem: add per-master stats to physmem
Added per-master stats (similar to cache stats) to physmem.
2012-06-05 01:23:11 -04:00
Geoffrey Blake
eced845a5e ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT 2012-06-05 01:23:11 -04:00
Chander Sudanthi
15228694d0 ARM: removed extra white space
Extra white space fixes in miscregs.hh
2012-06-05 01:23:10 -04:00
Chander Sudanthi
8a2ca2fd24 ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some
bootloaders/kernels care that it's set right. You can have a single
processor MP capable system, but you can't have a multi-processor
UP only system. This change also fixes the initialization of the MIDR
register.
2012-06-05 01:23:10 -04:00
Chander Sudanthi
e60b2ac706 ARM: PS2 encoding fix
Fixed Disable encoding and added SetDefaults.
See http://wiki.osdev.org/Mouse_Input for encodings.
2012-06-05 01:23:10 -04:00
Ali Saidi
70d7d6cc7f sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Ali Saidi
2e988bbab0 stats: Add stats unittest for total calculations. 2012-06-05 01:23:10 -04:00
Ali Saidi
6df196b71e O3: Clean up the O3 structures and try to pack them a bit better.
DynInst is extremely large the hope is that this re-organization will put the
most used members close to each other.
2012-06-05 01:23:09 -04:00
Ali Saidi
aec7a44116 sim: Add support for tcmalloc if it's installed and available.
This package is available in Ubuntu, Debian, and Redhat as google-perftools.
With multiple tests on a single machine I've seen a little over 10% performance
gain with tcmalloc.
2012-06-05 01:23:09 -04:00
Ali Saidi
1b370431d0 sim: Remove FastAlloc
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.
2012-06-05 01:23:08 -04:00
Ali Saidi
d6997777be ARM: Fix over-eager assert in gic. 2012-06-05 01:23:08 -04:00
Mitchell Hayenga
8294d49bb6 stats: Provide a mechanism to get a callback when stats are dumped.
This mechanism is useful for dumping output that is correlated with stats
dumping, but isn't tracked by the gem5 statistics.
2012-06-05 01:23:08 -04:00
Ali Saidi
0b0c5621ee ARM: Fix compilation on ARM after Gabe's change. 2012-06-05 01:23:08 -04:00
Gabe Black
008b17d816 ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
This eliminates a use of the ExtMachInst type outside of the ISAs.
2012-06-04 10:57:23 -07:00
Gabe Black
6437f3f4ee X86: Update stats for the CPUID change. 2012-06-04 10:43:11 -07:00
Gabe Black
35fa5074aa X86: Ensure that the CPUID instruction always writes its outputs.
The CPUID instruction was implemented so that it would only write its results
if the instruction was successful. This works fine on the simple CPU where
unwritten registers retain their old values, but on a CPU like O3 with
renaming this is broken. The instruction needs to write the old values back
into the registers explicitly if they aren't being changed.
2012-06-04 10:43:09 -07:00
Gabe Black
7b73c36f5d X86: Ensure that the decoder's internal ExtMachInst is completely initialized.
There are some bits of some fields of the ExtMachInst which are not actually
used for anything but are included in the hash of an ExtMachInst for
simplicity and efficiency. This change makes sure the decoder's internal
working ExtMachInst is completely initialized, even these unused bits, so that
there isn't any nondeterministic behavior, no valgrind messages about
uninitialized variables, and no potential false misses/redundant entries in
the decode cache.
2012-06-04 10:43:08 -07:00
Andreas Hansson
0d32940711 Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00
Andreas Hansson
fb9bfb9cfc Stats: Fix stats to match output after changeset 8800b05e1cb3
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of 8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.

changeset:   8983:8800b05e1cb3
user:        Nathan Binkert <nate@binkert.org>
summary:     stats: update stats for no_value -> nan
2012-05-09 11:52:14 -07:00
Andreas Hansson
1d520cda80 gcc: Small fixes to compile with gcc 4.7
This patch makes two very minor changes to please gcc 4.7. The
CopyData function no longer exists and this has been replaced. For
some reason previous versions of gcc did not complain on the const
char casting not having an implementation, but this is now addressed.
2012-05-30 05:31:48 -04:00
Andreas Hansson
b8cf48accc Bus: Remove redundant packet parameter from isOccupied
This patch merely remove the Packet* from the isOccupied member
function. Historically this was used to check if the packet was an
express snoop, but this is now done outside this function (where
relevant).
2012-05-30 05:31:11 -04:00
Andreas Hansson
5880fbe96d Bus: Turn the PortId into a transport function parameter
The main aim of this patch is to arrive at a suitable port interface
for vector ports, including both the packet and the port id. This
patch changes the bus transport functions
(recvFunctional/Atomic/Timing) to require a PortId parameter
indicating the source port. Previously this information was passed by
setting the source field of the packet, and this is only required in
the case of a timing request.

With this patch, the use of the source and destination field is also
more restrictive, as they are only needed for timing accesses. The
modifications to these fields for atomic snoops is now removed
entirely, also making minor modifications to the cache.
2012-05-30 05:30:24 -04:00
Andreas Hansson
cad802761a Packet: Unify the use of PortID in packet and port
This patch removes the Packet::NodeID typedef and unifies it with the
Port::PortId. The src and dest fields in the packet are used to hold a
port id (e.g. in the bus), and thus the two should actually be the
same.

The typedef PortID is now global (in base/types.hh) and aligned with
the ThreadID in terms of capitalisation and naming of the
InvalidPortID constant.

Before this patch, two flags were used for valid destination and
source, rather than relying on a named value (InvalidPortID), and
this is now redundant, as the src and dest field themselves are
sufficient to tell whether the current value is a valid port
identifier or not. Consequently, the VALID_SRC and VALID_DST are
removed.

As part of the cleaning up, a number of int parameters and local
variables are updated to use PortID.

Note that Ruby still has its own NodeID typedef. Furthermore, the
MemObject getMaster/SlavePort still has an int idx parameter with a
default value of -1 which should eventually change to PortID idx =
InvalidPortID.
2012-05-30 05:29:42 -04:00
Andreas Hansson
6a54f7fc5f Packet: Updated comments for src and dest fields
This patch updates the comments for the src and dest fields to reflect
their actual use. Due to a number of patches (e.g. removing the
Broadcast flag), the old comments are no longer indicative of the
current usage.
2012-05-30 05:29:07 -04:00
Andreas Hansson
3b367db42c Bridge: Split deferred request, response and sender state
This patch splits the PacketBuffer class into a RequestState and a
DeferredRequest and DeferredResponse. Only the requests need a
SenderState, and the deferred requests and responses only need an
associated point in time for the request and the response queue.

Besides the cleaning up, the goal is to simplify the transition to a
new port handshake, and with these changes, the two packet queues are
starting to look very similar to the generic packet queue, but
currently they do a few unique things relating to the NACK and
counting of requests/responses that the packet queue cannot be
conveniently used. This will be addressed in a later patch.
2012-05-30 05:28:06 -04:00
Gabe Black
d9988ded3c X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB. 2012-05-28 21:56:23 -07:00
Gabe Black
f91b06e20e X86: Add a 32 bit hello world test binary. 2012-05-27 19:01:09 -07:00
Gabe Black
40084e0c3e X86: Move the GDT down to where it can be accessed in 32 bit mode.
The GDT can be accessed by user level software running in compatibility mode
by moving segment selectors into segment registers. The GDT needs to be set up
at an address accessible in this mode.
2012-05-27 19:01:08 -07:00
Gabe Black
1d96135087 X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.
A small change was added a while ago to keep addresses from overflowing 32
bits when larger addresses shouldn't be accessible to software. That change
truncated when not in long mode, but really it should have truncated when not
in 64 bit mode. The difference is whether compatibility mode is included, a
mode that's supposed to act like a legacy 32 bit mode.
2012-05-27 19:01:04 -07:00
Gabe Black
19df4e94ee ISA,CPU: Generalize and split out the components of the decode cache.
This will allow it to be specialized by the ISAs. The existing caching scheme
is provided by the BasicDecodeCache in the GenericISA namespace and is built
from the generalized components.

--HG--
rename : src/cpu/decode_cache.cc => src/arch/generic/decode_cache.cc
2012-05-26 13:45:12 -07:00
Gabe Black
0cba96ba6a CPU: Merge the predecoder and decoder.
These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
2012-05-26 13:44:46 -07:00
Gabe Black
eae1e97fb0 ISA: Make the decode function part of the ISA's decoder. 2012-05-25 00:55:24 -07:00
Gabe Black
276f3e9535 CPU: Simplify the implementation of the decode cache.
Also reorganize it to make it more amenable to being rearranged later.
2012-05-25 00:54:39 -07:00
Gabe Black
82a228bd43 Decode: Make the Decoder class defined per ISA.
--HG--
rename : src/cpu/decode.cc => src/arch/generic/decoder.cc
rename : src/cpu/decode.hh => src/arch/generic/decoder.hh
2012-05-25 00:53:37 -07:00
Andreas Hansson
49da0497d3 Cache: Remove dangling doWriteback declaration
This patch removes the declaration of doWriteback as there is no
implementation for this member function.
2012-05-24 04:09:19 -04:00
Andreas Hansson
3e0ed08706 Packet: Cleaning up packet command and attribute
This patch removes unused commands and attributes from the packet to
avoid any confusion. It is part of an effort to clear up how and where
different commands and attributes are used.
2012-05-23 09:18:04 -04:00
Andreas Hansson
01906f957a Config: Use the attribute naming and include ports in JSON
This patch changes the organisation of the JSON output slightly to
make it easier to traverse and use the files. Most importantly, the
hierarchical dictionaries now use keys that correspond to the
attribute names also in the case of VectorParams (used to be
e.f. "cpu0 cpu1"). It also adds the name and the path to each
SimObject directory entry. Before this patch, to get cpu0, you would
have to query dict['system']['cpu0 cpu1'][0] and this could be a dict
with 'cpu0' : { cpu parameters }. Now you use dict['system']['cpu'][0]
and get { cpu parameters } (where one is "name" : "cpu0").

Additionally this patch includes more verbose information about the
ports, specifying their role, and using a JSON array rather than a
concatenated string for the peer.
2012-05-23 09:16:39 -04:00