Commit graph

11383 commits

Author SHA1 Message Date
Brandon Potter
3fa311e5ac syscall_emul: add many Linux kernel flags 2016-03-17 10:22:39 -07:00
Brandon Potter
b8688346a5 syscall_emul: rename OpenFlagTransTable struct
The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
2016-03-17 10:22:39 -07:00
Alexandru Dutu
75d6910607 syscall_emul: add extra debug support for syscalls
Breaks the debug output from system calls into two levels: Base and Verbose.
A macro is added specifically for system calls which allows developers to
easily add new debug messages in a consistent manner. The macro also contains
a field to print thread IDs along with the CPU ID.
2016-03-17 10:22:39 -07:00
Brandon Potter
c05fa16729 syscall_emul, style: refactor lseek 2016-03-17 10:22:39 -07:00
Brandon Potter
c47cf3ec20 syscall_emul, style: fix newline issue inside assert 2016-03-17 10:22:39 -07:00
Andreas Hansson
abcbc4e51e mem: Adjust cache queue reserve to more conservative values
The cache queue reserve is there as an overflow to give us enough
headroom based on when we block the cache, and how many transactions
we may already have accepted before actually blocking. The previous
values were probably chosen to be "big enough", when we actually know
that we check the MSHRs after every single allocation, and for the
write buffers we know that we implicitly may need one entry for every
outstanding MSHR.
* * *
mem: Adjust cache queue reserve to more conservative values

The cache queue reserve is there as an overflow to give us enough
headroom based on when we block the cache, and how many transactions
we may already have accepted before actually blocking. The previous
values were probably chosen to be "big enough", when we actually know
that we check the MSHRs after every single allocation, and for the
write buffers we know that we implicitly may need one entry for every
outstanding MSHR.
2016-03-17 09:51:22 -04:00
Andreas Hansson
7a40e7864a stats: Bump stats to match cache changes
Update stats to match current behaviour. As a result of the earlier
conflict check we are seeing a few prefetch requests being ignored
before being sent as upward snoops.
2016-03-17 09:51:21 -04:00
Andreas Hansson
041ea8107e mem: Create a separate class for the cache write buffer
This patch breaks out the cache write buffer into a separate class,
without affecting any stats. The goal of the patch is to avoid
encumbering the much-simpler write queue with the complex MSHR
handling. In a follow on patch this simplification allows us to
implement write combining.

The WriteQueue gets its own class, but shares a common ancestor, the
generic Queue, with the MSHRQueue.
2016-03-17 09:51:18 -04:00
Steve Reinhardt
f5d1dd75e5 stats: overdue updates to long regressions 2016-03-16 13:03:49 -07:00
Andreas Sandberg
d7f18fa6fa misc: Add a gitignore file based on the current hgignore
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-03-16 17:20:00 +00:00
Gabor Dozsa
d4c1600c4e misc: Fix argument handling for m5 initparam util 2016-03-16 16:23:42 +00:00
Nathanael Premillieu
f9cae4ae58 arm: Fix disasm printing
Fix the printDataInst function to properly print the immediate value.
2016-03-16 16:08:24 +00:00
Steve Reinhardt
b8c1e370fa scons: fix building in non-standard locations
It's apparently not widely known that our scons scripts allow you to
put the build directory wherever you want; not only does it not have
to be immediately under the root of your repo, it doesn't even have
to be underneath the root at all.  (For example, sometimes it's useful
to build on a local disk if your repo is on a slow NFS mount.)

I point this out because this functionality has been broken for close
to two years but no one seems to have noticed yet.  This patch fixes
an assumption that crept in in changeset be0e1724eb39 (May 09 2014)
that the build dir would be immediately under the top level of the
repo, preventing builds anywhere else.
2016-03-13 17:47:33 -07:00
Steve Reinhardt
807e2705b4 stats: update gpu-ruby-GPU_RfO stats
Output changed way back in this cset:

changeset:   11345:b6a66a90e0a1
user:        John Kalamatianos <john.kalamatianos@amd.com>
summary:     gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
2016-02-18 10:42:03 -05:00
Andreas Hansson
48d07b3fa3 configs: Add a lat_mem_rd style test script
This patch adds a config script that broadly replicates the behaviour
of lat_mem_rd. The test is based on traffic generators, and as such we
simply randomise addresses in increasingly large ranges, and play them
back using the trace functionality of the traffic generator.

The test script is accompanied by a post-processing and visualisation
script. At the moment no configurability is added to tweak the memory
hierarchy, but a follow on patch could easily extend the
functionality.
2016-03-08 17:51:02 -05:00
Andreas Hansson
fcbc208bb3 syscall_emul: Fix erroneous use of delete
clang correctly points out an erroneous use of delete.
2016-03-08 17:50:58 -05:00
David Guillen Fandos
c0c3316e31 sim: Add voltage() function to clocked_object
Adding voltage function which returns the current voltage
for a given clocked object. It's handy for power models and
similar stuff that need to retrieve voltage. Function
frequency() is already there, so I see no reason for not having
this one too.
2015-06-17 16:49:40 +01:00
Rekai Gonzalez Alberquilla
21f8242430 cpu: Change literal integer constants to meaningful labels
fu_pool and inst_queue were using -1 for "no such FU" and -2 for "all those
FUs are busy at the moment" when requesting for a FU and replying. This
patch introduces new constants NoCapableFU and NoFreeFU respectively.

In addition, the condition (idx == -2 || idx != -1) is equivalent to
(idx != -1), so this patch also simplifies that.

--HG--
extra : rebase_source : 4833717b9d1e09d7594d1f34f882e13fc4b86846
2015-05-05 16:47:24 +01:00
Andreas Hansson
8faeec44a6 base: Fix gpu-compute output stream creation
Match changes in output stream.
2016-03-04 20:14:10 -05:00
Andreas Sandberg
4f303785dc kvm: Shutdown KVM and disconnect performance counters on fork
We can't/shouldn't use KVM after a fork since the child and parent
probably point to the same VM. Knowing the exact effects of this is
hard, but they are likely to be messy. We also disconnect the
performance counters attached to the guest. This works around what
seems to be a kernel bug where spurious SIGIOs get delivered to the
forked child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Fatal if entering KVM in child process ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-27 14:52:10 +00:00
Andreas Sandberg
a91c1e69a8 sim: Add support for forking
This changeset adds forking capabilities to the gem5 python scripts. A fork
method is added to simulate.py. This method is responsible for forking the
simulator itself, and will direct all output files to a new output directory
based on the fork sequence number. The default name of the output directory is
the same as the parent with the suffix ".fN" added where N is the fork sequence
number. The fork method provides the option to specify if the system should be
drained prior to forking, or not. By default the system is drained to ensure
that there are no in-flight transactions.

When forking the simulator, the fork method returns the PID of the child
process, or returns 0 if running in the child. This is in line with the standard
Python forking interface.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Updated to comply with modern draining semantics ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:11:57 +00:00
Andreas Sandberg
6de52699bb dev: Add post-fork handling for disk images
This changeset adds support for notifying the disk images that the simulator has
been forked. We need to disable the saving of the CoW disk image from the child
process, and we need to make sure that systems which use a raw disk image are
not allowed to fork to avoid two or more gem5 processes writing to the same disk
image.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:11:52 +00:00
Andreas Sandberg
738d71f6a9 sim: Add support for notifying Drainable objects of a fork
When forking a gem5 process, some objects need to clean up resources
(mainly file descriptions) shared between the child and the parent of
the fork. This changeset adds the notifyFork() method to Drainable,
which is called in the child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:03:43 +00:00
Andreas Sandberg
5383e1ada4 base: Add support for changing output directories
This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.

This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-27 14:41:59 +00:00
Prakash Ramrakhyani
fed0ea55c4 util: update Java JNI interface to m5ops
Synchronize with
ab19693da "pseudo inst,util: Add optional key to initparam pseudo instruction"
2016-02-29 19:13:15 -06:00
Stephan Diestelhorst
f703160e5a mem, cpu: Add assertions to snoop invalidation logic
This patch adds assertions that enforce that only invalidating snoops
will ever reach into the logic that tracks in-order load completion and
also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds
some comments to MSHR::replaceUpgrades().
2015-08-10 11:25:52 +01:00
Krishnendra Nathella
cabd4768c7 cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
2015-07-19 15:03:30 -05:00
Mitch Hayenga
c0d19391d4 arm: Squash after returning from exceptions in v7
Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
2016-02-29 19:13:13 -06:00
Curtis Dunham
aa674268e9 base: support gzip-compressed object files 2016-02-29 19:13:13 -06:00
Andreas Hansson
28289e5995 stats: Update stats to reflect forwarding of InvalidateReq 2016-02-24 04:16:59 -05:00
Andreas Hansson
7958f34797 mem: Ensure that InvalidateReq is not forwarded as ReadExReq
This patch fixes an issue where an InvalidationReq only traversed one
level of the cache hierarchy, and was subsequently turned into a
ReadExReq due to it needing writable, and the command not being
checked for explicitly.
2016-02-24 04:16:57 -05:00
Matteo Andreozzi
496a8c6c92 cpu: TraceGen fix for tick frequency check
Bug fix for check on protobuf file frequency being different than
global frequency.

The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.
2016-02-24 04:16:55 -05:00
Andreas Sandberg
e2cea54deb dev, arm: Implement the NoMali reset callback
Add a callback handler for the NoMali reset callback. This callback is
called whenever the GPU is reset using the register interface or the
NoMali API. The callback can be used to override ID registers using
the raw register API.
2016-02-23 11:49:35 +00:00
Andreas Sandberg
81a8ce3564 dev, arm: Refactor the NoMali GPU
Refactor and cleanup the NoMaliGpu class:

  * Use a std::map instead of a switch block to map the parameter enum
    describing the GPU type to a NoMali type.

  * Remove redundant NoMali handle from the interrupt callback.

  * Make callbacks and API wrappers protected instead of private to
    enable future extensions.

  * Wrap remaining NoMali API calls.
2016-02-23 11:49:34 +00:00
Andreas Sandberg
826e0047b0 arm: Ship Linux device trees with gem5
Ship aarch32 and aarch64 device trees with gem5. We currently ship
device trees as a part of the gem5 Linux kernel repository. This makes
tracking hard since device trees are supposed to be platform dependent
rather than kernel dependent (Linux considers device trees to be a
stable kernel ABI). It also makes code sharing between aarch32 and
aarch64 impossible.

This changeset implements a set of device trees for the new
VExpress_GEM5_V1 platform. The platform is described in a shared file
that is separate from the memory/CPU description. Due to differences
in how secondary CPUs are initialized, aarch32 and aarch64 use
different base files describing CPU nodes and the machine's
compatibility property.
2016-02-23 11:21:07 +00:00
Andreas Hansson
4619f0ee8b scons: Add missing override to appease clang
Make clang happy...again.
2016-02-23 03:27:20 -05:00
Tony Gutierrez
5a88f0931f ruby: move range change send from RubyPort to derived classes. 2016-02-18 10:50:16 -05:00
John Kalamatianos
a28a234069 gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
Both Memory Fence is now flagged as Global Memory only to avoid resource
oversubscribing.
Flat instructions now check for Shared Memory resource busy to avoid
oversubscribing resources.
All WaitClass resources now use cycles (not ticks) to register the number
of pipe stages between Scoreboard and Execute to be consistent with
instruction scheduling logic which always used clock cycles.
2016-02-18 10:42:03 -05:00
Tony Gutierrez
9a0f1be21f gpu-compute: remove brig_object.hh from hsa_object.cc
brig_object.hh is specific to the HSAIL ISA, and hence should not be
included in ISA-agnostic code.
2016-02-17 11:46:02 -05:00
Tony Gutierrez
969babd26f ruby: send address ranges from RubyPort 2016-02-17 11:31:54 -05:00
Andreas Hansson
a34ff350da scons: Enable building with the gcc/clang Address Sanitizer
Allow the user to easily build gem5 with the Address Sanitizer, part
of both gcc and clang these days.
2016-02-17 03:56:20 -05:00
Andreas Hansson
0d50979888 misc: Add missing overrides to appease clang
Since the last round of fixes a few new issues have snuck in. We
should consider switching the regression runs to clang.
2016-02-15 03:40:32 -05:00
Andreas Hansson
407233f5d8 mem: Avoid using invalid iterator in cache lock list traversal
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
2016-02-15 03:40:04 -05:00
Michael LeBeane
b181cea364 ruby: make DMASequencer inherit from RubyPort
This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the
parent class of DMASequencer.  It removes redundant code and restores some
features which were lost when directly inheriting from MemObject.  For
example,
DMASequencer can now communicate to other devices using PIO, which is useful
for memmory-mapped communication between multiple DMADevices.
2016-02-14 20:28:48 -05:00
Michael LeBeane
2ae4cce393 configs: add command-line option to stop debug output
This patch adds a --debug-end flag to main.py so that debug output can be
stoped at a specified tick, while allowing the simulation to continue. It is
useful in situations where you would like to produce a trace for a region of
interest while still collecting stats for the entire run. This is in contrast
to the currently existing --debug-break flag, which terminates the simulation
at the tick.
2016-02-13 12:36:43 -05:00
Michael LeBeane
8d923c7380 syscall_emul: Implement clock_getres() system call
This patch implements the clock_getres() system call for arm and x86 in linux
SE mode.
2016-02-13 12:33:07 -05:00
Andreas Hansson
c6cede244b stats: Update stats to reflect changes to cache and crossbar 2016-02-10 04:08:27 -05:00
Andreas Hansson
83a5977481 mem: Be less conservative in clearing load locks in the cache
Avoid being overly conservative in clearing load locks in the cache,
and allow writes to the line if they are from the same context. This
is in line with ALPHA and ARM.
2016-02-10 04:08:25 -05:00
Andreas Hansson
92f021cbbe mem: Move the point of coherency to the coherent crossbar
This patch introduces the ability of making the coherent crossbar the
point of coherency. If so, the crossbar does not forward packets where
a cache with ownership has already committed to responding, and also
does not forward any coherency-related packets that are not intended
for a downstream memory controller. Thus, invalidations and upgrades
are turned around in the crossbar, and the memory controller only sees
normal reads and writes.

In addition this patch moves the express snoop promotion of a packet
to the crossbar, thus allowing the downstream cache to check the
express snoop flag (as it should) for bypassing any blocking, rather
than relying on whether a cache is responding or not.
2016-02-10 04:08:25 -05:00
Andreas Hansson
f84ee031cc mem: Align cache behaviour in atomic when upstream is responding
Adopt the same flow as in timing mode, where the caches on the path to
memory get to keep the line (if present), and we use the
responderHadWritable flag to determine if we need to forward the
(invalidating) packet or not.
2016-02-10 04:08:24 -05:00