arm: Ship Linux device trees with gem5
Ship aarch32 and aarch64 device trees with gem5. We currently ship device trees as a part of the gem5 Linux kernel repository. This makes tracking hard since device trees are supposed to be platform dependent rather than kernel dependent (Linux considers device trees to be a stable kernel ABI). It also makes code sharing between aarch32 and aarch64 impossible. This changeset implements a set of device trees for the new VExpress_GEM5_V1 platform. The platform is described in a shared file that is separate from the memory/CPU description. Due to differences in how secondary CPUs are initialized, aarch32 and aarch64 use different base files describing CPU nodes and the machine's compatibility property.
This commit is contained in:
Andreas Sandberg
parent
4619f0ee8b
commit
826e0047b0
63
system/arm/dt/Makefile
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63
system/arm/dt/Makefile
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@ -0,0 +1,63 @@
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# Copyright (c) 2015 ARM Limited
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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CPP?=cpp
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DTC?=dtc
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DTC_CPP_FLAGS=-nostdinc -undef
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TARGETS=\
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armv7_gem5_v1_1cpu.dtb armv7_gem5_v1_2cpu.dtb \
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armv7_gem5_v1_4cpu.dtb armv7_gem5_v1_8cpu.dtb \
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armv7_gem5_v1_16cpu.dtb \
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armv8_gem5_v1_1cpu.dtb armv8_gem5_v1_2cpu.dtb \
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armv8_gem5_v1_4cpu.dtb armv8_gem5_v1_8cpu.dtb \
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armv8_gem5_v1_16cpu.dtb
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GEN_DTS=mkdir -p .gen; \
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$(CPP) -x assembler-with-cpp \
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$(DTC_CPP_FLAGS) \
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-DCONF_PLATFORM=\"platforms/$(1)\" \
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-DCONF_CPUS=$(2) \
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-o $@ $<
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all: $(TARGETS)
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.gen/armv7_gem5_v1_%cpu.dts: armv7.dts platforms/vexpress_gem5_v1.dtsi
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$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
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.gen/armv8_gem5_v1_%cpu.dts: armv8.dts platforms/vexpress_gem5_v1.dtsi
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$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
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%.dtb: .gen/%.dts
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$(DTC) -I dts -O dtb -o $@ $<
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clean:
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$(RM) -r .gen
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$(RM) *.dtb
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143
system/arm/dt/armv7.dts
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143
system/arm/dt/armv7.dts
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@ -0,0 +1,143 @@
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/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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/dts-v1/;
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#include CONF_PLATFORM
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#define CPU(n) \
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cpu@ ## n { \
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device_type = "cpu"; \
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compatible = "gem5,arm", "arm,cortex-a15"; \
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reg = < n >; \
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};
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/ {
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model = "V2P-CA15";
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compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0x4 0x00000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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#if CONF_CPUS > 0
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CPU(0)
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#endif
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#if CONF_CPUS > 1
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CPU(1)
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#endif
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#if CONF_CPUS > 2
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CPU(2)
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#endif
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#if CONF_CPUS > 3
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CPU(3)
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#endif
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#if CONF_CPUS > 4
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CPU(4)
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#endif
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#if CONF_CPUS > 5
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CPU(5)
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#endif
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#if CONF_CPUS > 6
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CPU(6)
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#endif
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#if CONF_CPUS > 7
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CPU(7)
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#endif
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#if CONF_CPUS > 8
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CPU(8)
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#endif
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#if CONF_CPUS > 9
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CPU(9)
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#endif
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#if CONF_CPUS > 10
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CPU(10)
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#endif
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#if CONF_CPUS > 11
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CPU(11)
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#endif
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#if CONF_CPUS > 12
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CPU(12)
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#endif
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#if CONF_CPUS > 13
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CPU(13)
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#endif
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#if CONF_CPUS > 14
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CPU(14)
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#endif
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#if CONF_CPUS > 15
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CPU(15)
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#endif
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#if CONF_CPUS > 16
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#error Unsupported number of CPUs
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#endif
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};
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virt-encoder {
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compatible = "gem5,hdlcd-virt-encoder";
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port {
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hdlcd0_virt_input: endpoint@0 {
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remote-endpoint = <&hdlcd0_output>;
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};
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};
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display-timings {
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native-mode = <&timing0>;
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timing0: timing_1080p60 {
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/* 1920x1080-60 */
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <148>;
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hback-porch = <88>;
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hsync-len = <44>;
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vfront-porch = <36>;
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vback-porch = <4>;
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vsync-len = <5>;
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};
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};
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};
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};
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&hdlcd0 {
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status = "ok";
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port {
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hdlcd0_output: endpoint@0 {
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remote-endpoint = <&hdlcd0_virt_input>;
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};
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};
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};
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132
system/arm/dt/armv8.dts
Normal file
132
system/arm/dt/armv8.dts
Normal file
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@ -0,0 +1,132 @@
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/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
|
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
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* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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/dts-v1/;
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/memreserve/ 0x80000000 0x00010000;
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#include CONF_PLATFORM
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#define CPU(n) \
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cpu@ ## n { \
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device_type = "cpu"; \
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compatible = "gem5,armv8", "arm,armv8"; \
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reg = < n >; \
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enable-method = "spin-table"; \
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cpu-release-addr = <0 0x8000fff8>; \
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};
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/ {
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model = "V2P-AARCH64";
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compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0x4 0x00000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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#if CONF_CPUS > 0
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CPU(0)
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#endif
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#if CONF_CPUS > 1
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CPU(1)
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#endif
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#if CONF_CPUS > 2
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CPU(2)
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#endif
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#if CONF_CPUS > 3
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CPU(3)
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#endif
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#if CONF_CPUS > 4
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CPU(4)
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#endif
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#if CONF_CPUS > 5
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CPU(5)
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#endif
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#if CONF_CPUS > 6
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CPU(6)
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#endif
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#if CONF_CPUS > 7
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CPU(7)
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#endif
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#if CONF_CPUS > 8
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CPU(8)
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#endif
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#if CONF_CPUS > 9
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CPU(9)
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#endif
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#if CONF_CPUS > 10
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CPU(10)
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#endif
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#if CONF_CPUS > 11
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CPU(11)
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#endif
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#if CONF_CPUS > 12
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CPU(12)
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#endif
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#if CONF_CPUS > 13
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CPU(13)
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#endif
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#if CONF_CPUS > 14
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CPU(14)
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#endif
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#if CONF_CPUS > 15
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CPU(15)
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#endif
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#if CONF_CPUS > 16
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#error Unsupported number of CPUs
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#endif
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};
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};
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&hdlcd0 {
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status = "ok";
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display-timings {
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native-mode = <&timing0>;
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timing0: timing_1080p60 {
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/* 1920x1080-60 */
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clock-frequency = <148500>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <148>;
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hback-porch = <88>;
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hsync-len = <44>;
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vfront-porch = <36>;
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vback-porch = <4>;
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vsync-len = <5>;
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};
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};
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};
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186
system/arm/dt/platforms/vexpress_gem5_v1.dtsi
Normal file
186
system/arm/dt/platforms/vexpress_gem5_v1.dtsi
Normal file
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@ -0,0 +1,186 @@
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/*
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* Copyright (c) 2015-2016 ARM Limited
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* All rights reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Andreas Sandberg
|
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*/
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/ {
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arm,hbi = <0x0>;
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arm,vexpress,site = <0xf>;
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@2c001000 {
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compatible = "gem5,gic", "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
|
||||
timer {
|
||||
compatible = "arm,cortex-a15-timer",
|
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"arm,armv7-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
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<1 11 0xff01>;
|
||||
clocks = <&osc_sys>;
|
||||
clock-names="apb_pclk";
|
||||
};
|
||||
|
||||
pci {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
#address-cells = <0x3>;
|
||||
#size-cells = <0x2>;
|
||||
#interrupt-cells = <0x1>;
|
||||
|
||||
reg = <0x0 0x30000000 0x0 0x10000000>;
|
||||
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>,
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<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
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||||
|
||||
interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>,
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<0x000800 0x0 0x0 0 &gic 0 69 1>,
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<0x001000 0x0 0x0 0 &gic 0 70 1>,
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<0x001800 0x0 0x0 0 &gic 0 71 1>;
|
||||
|
||||
interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
/* Ths HDLCD controller driver hasn't reached mainline
|
||||
* yet. Disable it by default in the platform until the DT
|
||||
* bindings have stabilize.
|
||||
*/
|
||||
hdlcd0: hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0x0 0x2b000000 0x0 0x1000>;
|
||||
interrupts = <0 63 4>;
|
||||
clocks = <&osc_pxl>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
kmi@1c060000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x0 0x1c060000 0x0 0x1000>;
|
||||
interrupts = <0 12 4>;
|
||||
clocks = <&v2m_clk24mhz>, <&osc_smb>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@1c070000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x0 0x1c070000 0x0 0x1000>;
|
||||
interrupts = <0 13 4>;
|
||||
clocks = <&v2m_clk24mhz>, <&osc_smb>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
uart0: uart@1c090000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x1c090000 0x0 0x1000>;
|
||||
interrupts = <0 5 4>;
|
||||
clocks = <&osc_peripheral>, <&osc_smb>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@1c170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x0 0x1c170000 0x0 0x1000>;
|
||||
interrupts = <0 4 4>;
|
||||
clocks = <&osc_smb>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
|
||||
v2m_sysreg: sysreg@1c010000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0 0x1c010000 0x0 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc_pxl: osc@5 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <23750000 1000000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
osc_smb: osc@6 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 6>;
|
||||
freq-range = <20000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk6";
|
||||
};
|
||||
|
||||
osc_sys: osc@7 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 7>;
|
||||
freq-range = <20000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk7";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
arm,vexpress,site = <0>;
|
||||
|
||||
osc_peripheral: osc@2 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue