Commit graph

3249 commits

Author SHA1 Message Date
Kevin Lim
aa1efe3e72 Update this with the same option as single_fs.py
--HG--
extra : convert_revision : 778d654f515b6af7c45165b0a9bc5ef0d60f0d19
2006-06-16 18:04:34 -04:00
Kevin Lim
4e07f6ca52 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
2006-06-16 17:53:33 -04:00
Kevin Lim
0bbd909f02 Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
src/SConscript:
    Split off FuncUnits from old FUPool so I'm not including encumbered code.  This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
    Include the func unit file that's not in the encumbered directory.

--HG--
extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
2006-06-16 17:52:15 -04:00
Kevin Lim
def9ea38b5 Add in exec_context.hh, which is a file for documentation purposes only. It describes the ExecContext interface that the ISA uses to access CPU state. Also #ifdef Erik's old copy code from the decoder so ExecContext doesn't need his two specific copy functions.
src/arch/alpha/isa/decoder.isa:
    Surround Erik's old copy code with #ifdefs.  This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in).

--HG--
extra : convert_revision : 508ca387757a32bb616e5b4b07af17787a76970e
2006-06-16 17:19:36 -04:00
Kevin Lim
f4d0f92855 Miscellaneous minor fixes.
src/cpu/checker/cpu.cc:
    Add in comment.
src/cpu/cpuevent.hh:
    Fix up comment.
src/cpu/o3/bpred_unit.cc:
    Comment out Ozone instantiations.
src/cpu/o3/dep_graph.hh:
    Include destructor.

--HG--
extra : convert_revision : 549454ed11bc2fa49a0627f7fb8f96d00a9be303
2006-06-16 17:15:18 -04:00
Kevin Lim
baba18ab92 Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
2006-06-16 17:08:47 -04:00
Kevin Lim
720e6c4145 Checker updates.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
    Updates for checker.  Output more informative messages on error.  Rename some functions.  Add in option to warn (and not exit) on load results being incorrect.
src/cpu/checker/cpu_builder.cc:
src/cpu/checker/o3_cpu_builder.cc:
    Add in parameter to warn (and not exit) on load result errors.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Renamed checker functin.

--HG--
extra : convert_revision : d7aa28b8462691d20600f97a7213e2acd91c5665
2006-06-16 13:10:47 -04:00
Korey Sewell
51a5b82637 Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)
Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7
2006-06-15 22:01:28 -04:00
Ali Saidi
b1fc43dd59 Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 45677638b0bb5753f3277c212094cfb9313d4706
2006-06-15 15:05:26 -04:00
Steve Reinhardt
f06d508af0 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 8a1cd7ff43aa4ebbfce0ff174d2f4ba3f095dd47
2006-06-15 11:46:13 -04:00
Steve Reinhardt
88e22ee081 Get Port stuff working with full-system scripts.
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.

configs/test/fs.py:
    Add ".port" to busses to get a port reference.
    Get rid of commented-out code.
src/python/m5/__init__.py:
    resolveSimObject should call getCCObject() instead of createCCObject()
    to avoid cycles in recursively creating objects.
src/python/m5/config.py:
    Get rid of class/instance thing and go back to instance cloning.
    Deep copy has to happen only on instance cloning then (and not on subclassing).
    Add getCCObject() method to force creation of C++ SimObject without
    recursively creating its children.
    Add support for cloning port references (trickier than it sounds).
    Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
    Add ports.

--HG--
extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
2006-06-15 11:45:51 -04:00
Korey Sewell
74b9868c78 Mips Code Cleanup:
Fix some author stuff and copyright dates
Take out full system code

src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
    copyright info
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/control.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/process.cc:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/stacktrace.hh:
    copyright 2006
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
    copyright 2006
    take out full system
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/regfile.hh:
    copyright 2006
    use FloatRegVal
src/arch/mips/regfile/int_regfile.hh:
    copyright 2006
    move HI/LO to types.hh
src/arch/mips/types.hh:
    copyright 2006

    typedef FloatRegVal

--HG--
extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
2006-06-15 01:00:15 -04:00
Korey Sewell
1c55389578 tried to undo change and it didnt work so might as well put it back
--HG--
extra : convert_revision : 9793917e8a3e4d30f59ff469e4f08da96ce001f9
2006-06-14 22:01:36 -04:00
Korey Sewell
7b44630b95 change back, BK is acting up
--HG--
extra : convert_revision : 11fd5ebbca0408b357e9186d1b3722eb571e874e
2006-06-14 19:53:36 -04:00
Korey Sewell
7cd362ca4e add cycle to exit message
src/arch/mips/isa/formats/trap.isa:
    Take out fix that tried to fix trap
    instruction disassembly. It forces bad
    compile ..
configs/test/test.py:
    add 'cycle' to exit message

--HG--
extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
2006-06-14 19:45:15 -04:00
Korey Sewell
38ecb6a2ee -luxc1 fix
-noop templates
-trap disassembly

src/arch/mips/isa/decoder.isa:
    luxc1 uses doubleword, not single
src/arch/mips/isa/formats/int.isa:
    use new nop decode template
src/arch/mips/isa/formats/mem.isa:
    Noop templates
src/arch/mips/isa/formats/noop.isa:
    redo noop templates
src/arch/mips/isa/formats/trap.isa:
    fix for trap disassembly

--HG--
extra : convert_revision : 56f13e88abdcbd03ab828cff5d775c993157ae96
2006-06-14 19:31:21 -04:00
Ali Saidi
07e679fe85 add a comment that should be able to pass --help after config file
--HG--
extra : convert_revision : 0229d0c2f4f2615fa744561f32773b4c8160e81a
2006-06-14 16:12:56 -04:00
Korey Sewell
2a9becba44 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 9b5b1419e8e22bce16ed97fc02c2008ca0181afc
2006-06-14 14:43:45 -04:00
Kevin Lim
5d11e8bff6 Minor code cleanup of BaseDynInst.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Minor code cleanup by putting several bools into a bitset instead.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Changed around some things in BaseDynInst.

--HG--
extra : convert_revision : 1db363d69a863cc8744cc9f9ec542ade8472eb42
2006-06-14 13:12:41 -04:00
Steve Reinhardt
185ec39f79 Merge zizzer:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem

--HG--
extra : convert_revision : 6ebb12890c516a11733a04041f29c9964267a5ca
2006-06-13 23:19:42 -04:00
Steve Reinhardt
e981a97dec Move SimObject creation and Port connection loops
into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.

configs/test/fs.py:
configs/test/test.py:
    Rewrite for new port connector syntax.
src/SConscript:
    Remove unneeded files:
    - mem/connector.*
    - sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
    Allow getPort() to take an optional index to
    support vector ports (eventually).
src/python/m5/__init__.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
src/python/m5/config.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Add support for declaring and connecting MemObject
    ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
    Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
    ConfigNodes are gone; builder just gets the
    name of a .ini file section now.
src/sim/main.cc:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Split remaining initialization operations into two parts,
    loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
    SimObject resolution done globally in Python now
    (not via ConfigNode hierarchy).
src/sim/sim_object.cc:
    Remove unneeded #include.

--HG--
extra : convert_revision : 2fa4001eaaec0c9a4231ef6e854f8e156d930dfe
2006-06-13 23:19:28 -04:00
Kevin Lim
7709e6ba93 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 5c0e56572c5ca14e0c9a7ac52b0453026e48b336
2006-06-13 22:40:02 -04:00
Kevin Lim
133903b28d Add in a few global options. Feel free to rename them, they're just the first thing that came to mind.
src/python/m5/__init__.py:
    Add in a few global options.

--HG--
extra : convert_revision : e0dba78dd60f565a2e5cbda2cd6cf221bb3f4688
2006-06-13 22:39:31 -04:00
Kevin Lim
2f043aafbc Minor updates for stats.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch.hh:
    Update stats comments.
src/cpu/o3/fetch_impl.hh:
    Differentiate stats.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
    Update for stats.
src/cpu/o3/lsq.hh:
    LSQ now has stats.
src/cpu/o3/lsq_impl.hh:
    Register stats of all LSQ units.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Add in stats.

--HG--
extra : convert_revision : 7672ecf3c02515b268c28d5a986af1432197654a
2006-06-13 22:35:05 -04:00
Ali Saidi
285b88a57b allow long opts to m5 and add a help flag back.
--HG--
extra : convert_revision : 279cf97fe2e3098e2fe9c568c0336f97e41a14e4
2006-06-13 16:53:26 -04:00
Kevin Lim
dcf02c25e3 Make syscalls serialize after instructions so they work properly on the new CPU model.
--HG--
extra : convert_revision : c2cea5771e41d3c97d0e44559316363718d89abd
2006-06-13 14:39:05 -04:00
Kevin Lim
4ad3d47464 Add itb and dtb to checker when in full system mode.
--HG--
extra : convert_revision : 6e272d484d04b018e7d48e2878ae3e21e8dc571e
2006-06-13 14:37:50 -04:00
Kevin Lim
72e4b98b8d Add in DetailedCPU to test.
--HG--
extra : convert_revision : 98c67b45af239e1cf5bad6888da6577a4c3bb45d
2006-06-13 14:15:24 -04:00
Korey Sewell
e715e298e0 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 78ef94172884c2db0f591c54657b28be5be7f61c
2006-06-13 12:07:48 -04:00
Kevin Lim
66af2a7bf4 Merge ktlim@zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 1a00a3970c6064cb59cd2f788094569fc431bf70
2006-06-13 11:58:05 -04:00
Kevin Lim
7bcab0803f Compile fix.
--HG--
extra : convert_revision : 20649b0b9b9c496aae22c19926c1166c8c0cc821
2006-06-13 11:38:16 -04:00
Kevin Lim
6ee38f143e Merge ktlim@zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 349dbc2a39eba7fa5019c811123a643a41fdc6ff
2006-06-12 19:15:14 -04:00
Kevin Lim
b5cf61efad Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
2006-06-12 19:11:38 -04:00
Kevin Lim
6152e8abc3 Fix output messages.
src/cpu/o3/decode_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix output message.

--HG--
extra : convert_revision : f226b84d0e15f275286b1ed078d341831370322b
2006-06-12 19:05:48 -04:00
Kevin Lim
4acb283496 Clean up/shift some code around.
src/cpu/base_dyn_inst.cc:
    Clean up some code and update.
src/cpu/base_dyn_inst.hh:
    Clean up some code and update with more descriptive function names.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
    Remove unused parameters.
src/cpu/o3/commit_impl.hh:
    Remove unused parameters, also set squashCounter directly to the counted number of squashes.
src/cpu/o3/fetch_impl.hh:
    Update for function name changes.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
    Remove unused parameter, move some code into a function.

--HG--
extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
2006-06-12 19:04:42 -04:00
Kevin Lim
fbf3a82c5c Fix compile error.
--HG--
extra : convert_revision : 334f5033f5a3a303bfaec3a3acfbd36f205efe86
2006-06-12 18:59:24 -04:00
Kevin Lim
5639fb2c43 Fix memory leak.
src/arch/alpha/ev5.cc:
    Fix memory leak.  The faults are refcounted, but that only works if you're actually assigning them to a RefCountingPtr.

--HG--
extra : convert_revision : 9a57963eb5d5d86c16023bfedb0fb5ccdbe7efaa
2006-06-12 18:58:29 -04:00
Korey Sewell
07f21ce913 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 7ac7b9c9288e4940899766cd2dd55ef793d48d4d
2006-06-12 18:16:05 -04:00
Kevin Lim
841d0b9d40 Merge fixes to make full system compile and run.
src/arch/alpha/linux/system.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/sim/system.cc:
    Merge fixes.

--HG--
extra : convert_revision : aa3326c0ebf54da9ab1dbd2d9877da41ca487082
2006-06-12 17:53:57 -04:00
Kevin Lim
3e1537cf8b Removed syscall function from thread_context.hh. ThreadContext is the interface for external, non-CPU objects to access the thread, so they probably shouldn't be able to call syscall(). The case it was being used for was already handled by the ISA code.
src/arch/sparc/faults.cc:
src/cpu/thread_context.hh:
    Fix for merge problems.

--HG--
extra : convert_revision : 05a7a2d6e45099fcf36d113da2e52450d892a72c
2006-06-12 16:42:56 -04:00
Korey Sewell
b0fc2c02af Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 18a381fa230f2ef6d027359ffd619e3ae75cd446
2006-06-12 16:19:18 -04:00
Steve Reinhardt
babb22eea4 Fix python binary name in arch/SConscript.
Also delete no-longer-needed SPARC test.py files (should
have gone with my last chnageset where LiveProcess
became ISA-independent).

src/arch/SConscript:
    Mistakenly committed hard-coded python binary name.
    Should use same python to run isa_parser that was
    used to run scons.

--HG--
extra : convert_revision : a3acd5496f3b930d57bb59ae164b8a4a8065bbf8
2006-06-12 06:19:13 -04:00
Gabe Black
15a8f05060 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

src/arch/sparc/regfile.hh:
    Hand Merge

--HG--
extra : convert_revision : c47202689202069892524a7d71962082469996ee
2006-06-12 00:49:24 -04:00
Gabe Black
60a734e175 Made isHyperPriv and isPriv protected member variables.
--HG--
extra : convert_revision : af0c2bd46cdea31e5b7e6a75434bbd27b8e6b427
2006-06-12 00:44:24 -04:00
Nathan Binkert
df4b4f001e Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/newmem

--HG--
extra : convert_revision : e457e807b29d8ff88ac335cd50acd596e7e31eee
2006-06-11 23:02:50 -04:00
Nathan Binkert
3c95f5958f Merge iceaxe.:/Volumes/work/research/m5/head
into  iceaxe.:/Volumes/work/research/m5/merge

src/cpu/simple/base.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
    hand merge

--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : test/stattest.cc => src/unittest/stattest.cc
extra : convert_revision : 4bb576a2bf5e32784efc48030bd776c6c7c29a7c
2006-06-11 22:01:34 -04:00
Steve Reinhardt
e0140202bd Move LiveProcess::create() from arch-specific files
bcak to main LiveProcess, then automatically select
ISA based on object file type.  Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().

configs/test/test.py:
    Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
    Move create() from arch-specific files back to
    main LiveProcess, then automatically select ISA
    based on object file type.

--HG--
extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
2006-06-11 21:49:46 -04:00
Steve Reinhardt
d3a5783523 Add some utility functions to ease handling
SimObjects and sequences of SimObjects in a
uniform manner.

--HG--
extra : convert_revision : 5db28b778c6b1ca63ad0a112ad7e92cd610f64d3
2006-06-11 20:37:56 -04:00
Korey Sewell
13d46e2075 Remove Full System Files
src/arch/mips/SConscript:
    remove full-system
src/arch/mips/stacktrace.hh:
    alpha to mips

--HG--
extra : convert_revision : 5aa7ba6a4af4884e911708608dfc5a552f70654d
2006-06-11 19:04:22 -04:00
Ali Saidi
4ab8e881ed Fix compiling for SPARC_SE:
- change include from exec_context.hh -> threadcontext.hh
- g++ 4.0.3 complaint about broken code (which it was).
- bad merge thread_context -> exec_context

src/arch/sparc/isa/includes.isa:
    Fix SPARC_SE for exec_context->thread_context switch
src/arch/sparc/regfile.hh:
    fix g++ 4.0.3 complaint about broken code (which it was).
src/cpu/thread_context.hh:
    fix bad merge

--HG--
extra : convert_revision : f5bab822d5c25177756e9890e143b0ad8d704201
2006-06-11 17:21:02 -04:00