Commit graph

242 commits

Author SHA1 Message Date
Korey Sewell
2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-13 16:58:16 -05:00
Ali Saidi
5a4fc93fca Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if that isn't set use cwd.
--HG--
extra : convert_revision : 6548dd6de376dd59285a37a03bcf2525f8fc3845
2007-11-03 14:41:00 -04:00
Ali Saidi
51345d7324 Checkpoints: Change Simulation.py to not go crazy if the simulation ends before the number of checkpoints requested are created.
--HG--
extra : convert_revision : 865179134a219b34dbbba698e1fa0da7c452e074
2007-10-25 22:20:00 -04:00
Ali Saidi
a630d77ec5 Configuration: Move iocache outside of processors loop so it works for MP systems
--HG--
extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
2007-10-08 15:19:58 -04:00
Gabe Black
847a18ad48 X86: Adjust the config scripts for x86 fs.
--HG--
extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
2007-10-07 17:52:36 -07:00
Ali Saidi
136cb057d4 Checkpointing: Fix directory regex
--HG--
extra : convert_revision : 4d3958eda66209373249e54e7deadd1a7442e828
2007-09-12 15:27:15 -04:00
Ali Saidi
6f9ad931cc Checkpointing: Force drain/resume when switching a CPU
--HG--
extra : convert_revision : 7d9c3f4c8c357e3a9214deba5df3581beeaf7cb6
2007-09-12 15:24:24 -04:00
Ali Saidi
dd6a21190e Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters.
Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]

--HG--
extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd
2007-09-05 14:57:50 -04:00
Ali Saidi
bba265ccd8 PCI: Move PCI Configuration data into devices now that we can inherit parameters.
--HG--
extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
2007-08-16 16:49:05 -04:00
Ali Saidi
773cb77656 Devices: Make EtherInts connect in the same way memory ports currently do.
--HG--
extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
2007-08-16 16:49:02 -04:00
Ali Saidi
e9ddc7fbca Regression: fix configuration for SPARC_FS
--HG--
extra : convert_revision : 88aa9649cc1b4d8165616e98880d3d6cd2a75762
2007-08-12 19:44:04 -04:00
Vincentius Robby
ec4000e0e2 Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-08 18:43:12 -04:00
Ali Saidi
06a9f58c68 DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-10 16:14:01 -04:00
Steve Reinhardt
3afc625975 merge from head
--HG--
extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
2007-08-03 03:51:30 -04:00
Ali Saidi
31a9114a3d merge, no manual changes
--HG--
extra : convert_revision : 8504bddf1f73a4186cebc03c3e52e42ea38361fc
2007-08-02 15:38:06 -04:00
Gabe Black
e719a3e4c0 Fix how the "cmd" parameter is set in se.py and remove hack in x86 process initialization code.
--HG--
extra : convert_revision : 1fc741eea956ebfa4cef488eef4333d1f50617a6
2007-08-01 18:19:23 -07:00
Ali Saidi
456a4570c1 Configuration: Update the drive systems kernel as well as the testsys kernel with cmd line option.
--HG--
extra : convert_revision : 5dfb0db65452c0b7aa3e2dc2a0209e3f8e23811f
2007-08-01 17:39:16 -04:00
Steve Reinhardt
884807a68a Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work.  Timing is closer but not there yet.

--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15 20:11:06 -07:00
Steve Reinhardt
9172876dd7 Fix problem with unset max_loads in memtest.
Also make default 0, and make that mean run forever.

--HG--
extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
2007-07-15 14:32:55 -07:00
Steve Reinhardt
b1bdc3b3d9 Punt on old -n/-c memtest args.
Also added comments to document treespec format.

--HG--
extra : convert_revision : fa9e8f66b68b96a4efca8a7fe6e7c37367382d9d
2007-07-15 14:07:31 -07:00
Steve Reinhardt
ad560a6642 Add --force-bus option to memtest.py.
--HG--
extra : convert_revision : 101735cca426903704ff2edaff051fa7c5bfc46c
2007-07-15 13:22:49 -07:00
Steve Reinhardt
4bcfa916f1 New tree-based algorithm for creating more complex cache hierarchies.
--HG--
extra : convert_revision : de8dd4ef5dae0f3e084461e8ef7c549653e61d3f
2007-07-14 23:49:24 -07:00
Steve Reinhardt
07f091d6ed Get rid of remaining traces of obsolete CoherenceProtocol object.
--HG--
extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
2007-06-30 17:59:45 -07:00
Steve Reinhardt
9117c94f9c Get rid of coherence protocol object.
--HG--
extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-27 20:54:13 -07:00
Steve Reinhardt
83af0fdcf5 Getting closer...
configs/example/memtest.py:
    Add progress interval option.
src/base/traceflags.py:
    Add MemTest flag.
src/cpu/memtest/memtest.cc:
    Clean up tracing.
src/cpu/memtest/memtest.hh:
    Get rid of unused code.

--HG--
extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21 11:59:17 -07:00
Steve Reinhardt
d69a763833 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

configs/example/memtest.py:
    Hand merge redundant changes.

--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17 17:30:24 -07:00
Steve Reinhardt
35cf19d441 More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
    Revamp options.
src/cpu/memtest/memtest.cc:
    No need for memory initialization.
    No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
    MemTest really doesn't want to snoop.
src/mem/bridge.cc:
    checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
    More major reorg.  Seems to work for atomic mode now,
    timing mode still broken.

--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-17 17:27:53 -07:00
Nathan Binkert
d14256f9ba the cmd argument is supposed to be an array of parameters, not one string
--HG--
extra : convert_revision : dffdaa94a1f28f3709515a9eeed420552d8c7b22
2007-06-10 13:57:48 -07:00
Nathan Binkert
e9936a6250 More realistic parameters
--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-06-09 22:43:08 -07:00
Ali Saidi
48133a0f04 fix SPARC....
configs/common/FSConfig.py:
    fix SPARC

--HG--
extra : convert_revision : 34a36c0f626f3fb8a1526ec194a9b0cdae32fed4
2007-06-04 12:03:38 -04:00
Nathan Binkert
35147170f9 Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-27 19:21:17 -07:00
Steve Reinhardt
9f1c104ccd memtest.py:
Make clocks more reasonable.
Fix bug in sense of options.timing flag.

configs/example/memtest.py:
    Fix bug in sense of options.timing flag.
configs/example/memtest.py:
    Make clocks more reasonable.

--HG--
extra : convert_revision : 3715697988c56e92a4da129b42026d0623f5e85e
2007-05-22 06:22:27 -07:00
Steve Reinhardt
0305159abf PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-19 00:24:34 -04:00
Ali Saidi
0934f259d6 add an l2 cache option to se example config
configs/common/Options.py:
configs/example/fs.py:
    move l2 cache option to Options.py

--HG--
extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8
2007-05-15 18:06:35 -04:00
Ali Saidi
f317227b4e hopefully the final hacky change to make the bus bridge work ok
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
    hopefully the final hacky change to make the bus bridge work ok

--HG--
extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-15 17:39:50 -04:00
Ali Saidi
57104ea5f9 couple more bug fixes for intel nic
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
    couple more bug fixes

--HG--
extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
2007-05-14 16:37:00 -04:00
Ali Saidi
634d2e9d83 remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
    set the latency parameter in terms of a latency
configs/common/FSConfig.py:
    give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
    remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    add caches to tsunami-simple configs

--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-10 18:24:48 -04:00
Ali Saidi
0dfc29a023 fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-07 14:42:03 -04:00
Ali Saidi
6e60d5c12f add a udp stream benchmark and a udp loopback benchmark
--HG--
extra : convert_revision : 9300c67a1258e57436eba6cbdbed8fdf93fb6e59
2007-04-30 13:08:21 -04:00
Ali Saidi
e77aa3d212 make ping actually end
--HG--
extra : convert_revision : 6932d050a821abc7871bc73051688a986dcea364
2007-04-30 13:07:05 -04:00
Kevin Lim
522e59840f Fix mutex test script for latest disk image.
--HG--
extra : convert_revision : 1b0a251046674db1be8c9a2c026ff8c17f9cea06
2007-04-26 00:10:06 -04:00
Ron Dreslinski
c47804002a Fix the splash2 run script
--HG--
extra : convert_revision : 2b5f6718ac93d3d1b9b1d1b290f1ff5fa10cd0d8
2007-04-23 16:03:53 -04:00
Lisa Hsu
25e92383c8 spec-surge-client.rcS:
fix script to reflect new benchmark directory sturcture

configs/boot/spec-surge-client.rcS:
    fix script to reflect new benchmark directory sturcture

--HG--
extra : convert_revision : 45f9d8aebabd1f3f8d1e826e07840e2365511a35
2007-04-20 20:21:59 -04:00
Gabe Black
39c4ea3473 Fix mcf benchmark object so it gets the arguments it expects.
--HG--
extra : convert_revision : 47087be1f89699e9f8e0dc023abbf593bc0f6618
2007-03-22 00:10:47 -04:00
Nathan Binkert
d55b25cde6 Move all of the parameters of the Root SimObject so they are
directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-06 11:13:43 -08:00
Ali Saidi
82874eefca Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03 19:03:22 -05:00
Ali Saidi
1694c65ba1 Add Iob and remove the fake device
configs/common/FSConfig.py:
    add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy

--HG--
extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03 19:02:31 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Gabe Black
4b4b46ea90 Keep around which input set was used for a benchmark, and make vortex work with SPARC.
--HG--
extra : convert_revision : c891435a31e81fb8294484aedf340c0c96c8afa2
2007-03-03 03:34:53 +00:00
Nathan Binkert
fa4c3d74fe Get rid of the ConsoleListener SimObject and just fold the
relevant code directly into the SimConsole object.  Now,
you can easily turn off the listen port by just specifying
0 as the port.

--HG--
extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-21 22:14:11 -08:00