change getPort parameter from char* to string
Add an extra phase between construction and init called connect
SConscript:
Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
the connection to memory shouldn't be made until we know the memory
object exists (e.g. after construction)
dev/io_device.hh:
change to const string
mem/bus.hh:
change getPort parameter from char* to string
initialize num_interfaces
mem/mem_object.hh:
change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
change getPort parameter from char* to string
get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Add an extra phase between construction and init called connect
--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
on execution.
configs/test/test.py:
Move test binary out of m5-test, don't depend on
m5-test/Benchmarks.
python/m5/objects/System.py:
Split out full-system-only parameters (lost in merge).
sim/system.cc:
Need to be able to instantiate System directly in SE mode
(lost in merge).
sim/system.hh:
A few more functions here are FS-only.
configs/test/hello:
Add in binary.
--HG--
rename : configs/test.py => configs/test/test.py
extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395
use Receive side scaling
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
add support for setting the RSS flag to notify the driver
to use RSS
--HG--
extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041
See configs/test.py for test config (using simple
binary in my home directory on zizzer).
base/chunk_generator.hh:
Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
Fix roundDown to take integer alignments.
cpu/base.cc:
Register exec contexts regardless of state (not sure why
this check was in here in the first place).
mem/physical.cc:
Add breaks to switch.
python/m5/objects/BaseCPU.py:
Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
HierParams is gone.
python/m5/objects/PhysicalMemory.py:
mmu param is full-system only.
sim/process.cc:
Stack mapping request must be page-aligned and page-sized.
Don't delete objFile object in create since we are counting
on it being around for startup().
--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
SConscript:
Add Back memory to be built
mem/physical.hh:
Fix function declerations
python/m5/objects/BaseCPU.py:
Remove IL1 and DL1 params from the cpu object
--HG--
extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9
Ready to start testing if I could fix the linking errors I can't ever seem to fix.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add connecting of ports until builder can handle it.
mem/physical.cc:
Add function to allocate a port in the object
Remove some full_sys stuff untill needed
mem/physical.hh:
Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
Update the params
sim/process.cc:
Make sure to use the right name (hopefully CPU constructor already called)
--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
Clean out old memory python files, move them into old_mem directory. Maybe we should just delete them, they are under revision control.
Add new py files for new objects.
SConscript:
Update because memory is just a header file now
base/chunk_generator.hh:
Make Chunk Generator return the entire size if the chunk_size is set to zero. Useful when trying to chunck on blocksize of memory, which can write large pieces of data.
cpu/simple/cpu.cc:
Make sure to delete the pkt.
mem/physical.cc:
mem/physical.hh:
Set up response event.
mem/port.cc:
Rename rqst to req to conform to same standard naming convention.
python/m5/objects/PhysicalMemory.py:
Update the params, inheritence
--HG--
extra : convert_revision : 857154ec256522baf423b715833930497999549b
until the cache access occurs. The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
get rid of pio_delay write and the associated code to move
the write to the cache access function
dev/sinicreg.hh:
no more write delays
python/m5/objects/Ethernet.py:
get rid of pio_delay write
--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
Take System argument in constructor.
cpu/exec_context.cc:
Take System argument in constructor.
Merge two constructors into a single one.
cpu/exec_context.hh:
Take System argument in constructor.
Merge two constructors into a single one.
Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
Segregate full-system only Process parameters (most of them!).
sim/process.cc:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
Generate ProxyMemory object to pass to loader for transparent
virtual page allocation.
sim/process.hh:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
sim/system.cc:
sim/system.hh:
Enable System object for non-full-system too.
Basically involved putting most of the existing code
inside '#ifdef FULL_SYSTEM'.
Key thing needed for syscall emulation at this point is
the PhysicalMemory object (for Process initialization).
--HG--
extra : convert_revision : f0f34b47bd4f77b502191affd3d03b4d6d9bcdd8
separate the rx thread and tx thread and get rid of the dedicated flag.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
dedicated flag goes away, we have new individual flags for
rx thread and tx thread
dev/sinic.cc:
Virtualize sinic
- The io registers are replicated many times in memory, allowing the NIC to
differentiate among several virtual interfaces.
- On the TX side, this allows multiple CPUs to initiate transmits at the same
time without locking in the software. If a partial packet is transmitted,
then the state machine blocks waiting for that virtual interface to complete
its packet. Then the state machine will move on to the next virtual
interface. The commands are kept in fifo order.
- On the RX side, multiple partial transmits can be simultaneously done.
Though a packet does not deallocate its fifo space until all preceeding
packets in the fifo are deallocated. To enable multiple receives, it
is necessary for each virtual nic to keep its own information about its
progress through the state machine.
dev/sinic.hh:
Virtualize sinic
Receive state must be virtualized since we allow the receipt of packets in
parallel.
dev/sinicreg.hh:
Virtualize sinic
separate rx thread and tx thread
create a soft interrupt and add a command to trigger it.
pad out the reserved bits in the RxDone and TxDone regs
--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
dev/ns_gige.cc:
add support for delaying pio writes until the cache access occurs
the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
the txPioRequest and rxPioRequest things were more or less bogus
add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
Add delay_read and delay_write to the register information struct
for now, we won't delay any reads, and we'll delay the writes that
initiate DMAs
python/m5/objects/Ethernet.py:
add a parameter to delay pio writes until the timing access
actually occurs.
--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
python/m5/config.py:
Clock should not be a NumericParamValue since math on it can be
ambiguous. (As the comment clearly says.)
--HG--
extra : convert_revision : 74f8ec846c6a980d92e0bf4bf1c7fac73a75b923
python/m5/config.py:
Make Clock a NumericParamValue so you can do math with it
--HG--
extra : convert_revision : 7fa548d1a23c604a31d3ecae3853949b064a1830
can specify either independently.
python/m5/objects/Device.py:
io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently.
dma_bus defaults to point to whatever pio_bus uses.
--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
losing type information.
python/m5/config.py:
Allow math on CheckedInt-derived ParamValue classes w/o
losing type information.
- Make CheckedInt derive from NumericParamValue, and *not*
multiply inherit from long
- Move CheckedInt bounds check to _check() hook so we can
call it when value is updated (not just in constructor)
python/m5/convert.py:
- make toInteger() return a long, making toLong() unnecessary
- toMemorySize should return long rather than float
--HG--
extra : convert_revision : c1cf5e15b9ff35d9b573dd545e076fe68afef989
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us
dev/ns_gige.cc:
Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
Shuffle around parameters to make it easier to find stuff
rename cycleTime -> clock
dev/sinic.hh:
rename cycleTime -> clock
--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7
dev/ns_gige.cc:
stop exposing the m5reg to the configuration stuff and build it
based on exposed flags. Expose dedicated now.
dev/ns_gige.hh:
goodbye m5reg hello dedicated
dev/ns_gige_reg.h:
Flags for the M5REG
--HG--
extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
stay fixed even if the path to the binary changes, so the simulation results
are independent of that path.
--HG--
extra : convert_revision : d1109cd284466c14eddc97289908a51e771fc5db
dev/etherdump.cc:
no default parameters anymore they should be in python
python/m5/objects/Ethernet.py:
move the maxlen parameter for EtherDump into python
--HG--
extra : convert_revision : a796353a68907dfeb22059cd3ad536e6e8f60998
For example, 'scons ALPHA_SE/test/opt/quick' will build
ALPHA_SE/m5.opt if necessary and run all the self-identified
"quick" tests on it. Other possibilities:
- Run just test1: scons ALPHA_SE/test/opt/test1
- Run all tests: scons ALPHA_SE/test/opt
- Run all tests on debug build: scons ALPHA_SE/test/debug
- Update test1 reference outputs in m5-test:
scons update_ref=y ALPHA_SE/test/opt/test1
The proper tests will be selected based on the setting
of FULL_SYSTEM, ALPHA_TLASER, etc.
README:
Update directions to use scons-based test invocation.
SConscript:
Return list of generated build environments to SConstruct
so it can associate tests with each of them.
Set 'M5Binary' attribute on each env to record name of
generated binary to be tested.
build/SConstruct:
- Support invoking m5-test tests via scons.
- Add new non-sticky option category, for 'update_ref'.
- Move existing "sticky" option definitions out of
build_dir loop. Someday we can generate help text
from these.
- Make 'CC' and 'CXX' sticky options; use environment vars as
defaults if available.
- Make config builder more scons-y.
python/m5/__init__.py:
Make AddToPath() correctly handle relative path arguments.
Assumes that sys.path[0] has the directory where the current
Python file lives; new m5execfile() function sets this up
properly for exec'd files.
--HG--
extra : convert_revision : 48896688592e210d8e63f96c34e57474853d0e66
from Latency to Tick, and rename max_time to max_tick.
python/m5/objects/Root.py:
sim/root.cc:
Convert type of max_time and progress_interval
from Latency to Tick, and rename max_time to max_tick.
--HG--
extra : convert_revision : 2f2aacf6321c3003a0ce834acd8fb726abf27ce3
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
python/m5/config.py:
NextEthernetAddr shouldnt' be a Singleton since we want __init__ to be
called more than once.
Make the EthernetAddr class a "proxy" so that unproxy will
be called and NextEthernetAddr will generally work correctly.
--HG--
extra : convert_revision : c89bf268e805e202ae71030fcea4833867c7e477
Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.
cpu/base.cc:
pass the desired cpu_id into registerExecContext, offsetting it
by the thread number. a cpu_id of -1 means that it should be
generated for you.
cpu/base.hh:
Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
Accept the cpu_id as a parameter
while we're here, let's remove the multiplier since it is
not used.
dev/alpha_console.cc:
don't take the number of CPUs as a parameter. Calculate it from
the system based on the number of CPUs that have been registered.
move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
don't take the number of CPUs as a parameter.
move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
take the cpu_id as a parameter. Default it to -1 which means
that it will be generated.
sim/system.cc:
allow the registerExecContext functioin to take a desired
cpu_id as a parameter. Check to ensure that the id isn't
already used. Accept -1 as a request to have an id assigned.
sim/system.hh:
keep track of the number of registered exec contexts.
provide a function for accessing the number of exec contexts
that checks to ensure that they are all registered correctly.
--HG--
extra : convert_revision : 8e12f96ff8a49fa16cdbbdb4c05c651376c35788
the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.
dev/ns_gige.cc:
Implement a state machine clock that acutally limits how fast
the state machine can run. After each state transition, a
variable is kept to hold the next state transition until the
next clock. The frequency is of the actual state transitions,
and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
Default the state machine clock to '0ns' so the default
behaviour doesn't change when we actually implement the
state machine clock.
--HG--
extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd
Fixed printing so the tokenizer in m5 doesn't get confused
Expanded NullSimObject so it could be used as an element in a VectorParam
--HG--
extra : convert_revision : 661b1916967d663ab7aee891f15f7ca190deeba6
object and get rid of the ParamContext that each used to have.
python/m5/objects/Root.py:
Add max_time and progress_interval to the Root object
sim/root.cc:
Add max_time and progress_interval to the Root object. These
parameters used to be in their own contexts in sim_events.cc
sim/sim_events.cc:
Get rid of the ParamContext for max cycles and the progress
event. Move the functionality to the Root object
sim/sim_events.hh:
Move ProgressEvent declaration to the header so that it can
be used in other files.
--HG--
extra : convert_revision : ff664b806855e8eb9201b8a25392aa53204464f0
