Commit graph

11170 commits

Author SHA1 Message Date
Andreas Hansson
2ac04c11ac misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
2015-10-12 04:08:01 -04:00
Andreas Hansson
22c04190c6 misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
2015-10-12 04:07:59 -04:00
Joel Hestness
735c4a8766 stats: Update for UDelayEvent quiesce change 2015-10-10 16:45:41 -05:00
Joel Hestness
1f2e7c1aaa sim: Don't quiesce UDelayEvents with 0 latency
ARM uses UDelayEvents to emulate kernel __*udelay functions and speed up
simulation. UDelayEvents call Pseudoinst::quiesceNs to quiesce the system for
a specified delay. Changeset 10341:0b4d10f53c2d introduced the requirement
that any quiesce process that is started must also be completed by scheduling
an EndQuiesceEvent. This change causes the CPU to hang if an IsQuiesce
instruction is executed, but the corresponding EndQuiesceEvent is not
scheduled.

Changeset 11058:d0934b57735a introduces a fix for uses of PseudoInst::quiesce*
that would conditionally execute the EndQuiesceEvent. ARM UDelayEvents specify
quiesce period of 0 ns (src/arch/arm/linux/system.cc), so changeset 11058
causes these events to now execute full quiesce processes, greatly increasing
the total instructions executed in kernel delay loops and slowing simulation.

This patch updates the UDelayEvent to conditionally execute
PseudoInst::quiesceNs (**a quiesce operation**) only if the specified
delay is >0 ns. The result is ARM delay loops no longer execute instructions
for quiesce handling, and regression time returns to normal.
2015-10-10 16:45:38 -05:00
Rekai Gonzalez Alberquilla
d3d159749a isa: Add parameter to pick different decoder inside ISA
The decoder is responsible for splitting instructions in micro
operations (uops). Given that different micro architectures may split
operations differently, this patch allows to specify which micro
architecture each isa implements, so different cores in the system can
split instructions differently, also decoupling uop splitting
(microArch) from ISA (Arch). This is done making the decodification
calls templates that receive a type 'DecoderFlavour' that maps the
name of the operation to the class that implements it. This way there
is only one selection point (converting the command line enum to the
appropriate DecodeFeatures object). In addition, there is no explicit
code replication: template instantiation hides that, and the compiler
should be able to resolve a number of things at compile-time.
2015-10-09 14:50:54 -05:00
Dylan Johnson
7624fc1fb4 sim: Add relative break scheduling
Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
2015-10-09 14:27:09 -05:00
Steve Reinhardt
90c279e4b1 arch: clean up isa_parser error handling
Although some decent error messages were getting generated inside
isa_parser.py, they weren't always getting printed because of the
screwy way we were handling exceptions.  (Basically an inner
exception would get hidden by an outer exception, and the more
informative inner error message would not get printed.)

Also line numbers were messed up, since they were taken from the
lexer, which is typically a token (or more) ahead of the grammar
rule that's being matched.  Using the 'lineno' attribute that
PLY associates with the grammar production is more accurate.
The new LineTracker class extends lineno to track filenames as
well as line numbers.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
2511490c9c sim: add ExecMacro to Exec* compound debug flags
Really should have been there in the first place, IMO.
Makes debugging x86 execution a lot easier.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
4b7c1fe610 sim: print pid in output header
This information is useful if you have a bunch of simulations running
and want to know which one to kill, but you've neglected to take
advantage of the previous patch and embed the pid in your output path.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
a2c875c746 x86: implement rcpps and rcpss SSE insts
These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.

This code was basically developed by copying the code for
sqrtps and sqrtss.  The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
57b9f53afa x86: implement fild, fucomi, and fucomip x87 insts
fild loads an integer value into the x87 top of stack register.
fucomi/fucomip compare two x87 register values (the latter
also doing a stack pop).
These instructions are used by some versions of GNU libstdc++.
2015-10-06 17:26:50 -07:00
Curtis Dunham
83e07c07f9 ext: fix SST connector
The renamings in changesets 8f5993cf (2015-03-23) "mem: rename
Locked/LOCKED to LockedRMW/LOCKED_RMW" and fdd4a895 (2015-07-03)
"mem: Split WriteInvalidateReq into write and invalidate" broke the
SST connector.  This commit repeats those renamings in ext/sst.
2015-10-06 18:08:28 -05:00
Dylan Johnson
71b1c6ce76 sim: Add ability to break at specific kernel function
Adds a GDB callable function that sets a breakpoint at
the beginning of a kernel function.
2015-09-02 13:34:19 -05:00
Andreas Sandberg
17dbb49294 tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.

--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
2015-10-05 13:13:23 -05:00
Steve Reinhardt
d1811cc6cf stats: update EIO stats for snoop filter changes 2015-10-02 01:04:12 -04:00
Andreas Hansson
7dd171ba96 config: Fix 'learning gem5' configs after SMT push
This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.
2015-10-01 04:07:15 -04:00
Curtis Dunham
02881a7bf3 base: remove Trace::enabled flag
The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.
2015-09-30 15:21:55 -05:00
Mitch Hayenga
ccf4f6c3d7 arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is
detected.  Having 2 SMT threads share a TLB resulted in these not being
updated as required.  This patch adds a thread context identifer to
assist in the invalidation of these variables.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
9e07a7504c cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
a5c4eb3de9 isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
e255fa053f arm: SMT MPIDR Setting
Changes assignment of the MPIDR for multi-threaded systems only.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
fafa83ed32 cpu: Add per-thread monitors
Adds per-thread address monitors to support FullSystem SMT.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
582a0148b4 config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
52d521e433 cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
cores) caused failures due to the CPU id assignment logic.  The comment
about thread assignment (worrying about core 0 not having tid 0) seems
not to be valid given that our configuration scripts initialize them in
order.

This removes that constraint so a heterogenously threaded sytem can work.
2015-09-30 11:14:19 -05:00
Joel Hestness
c05d268cfa ruby: Fix CacheMemory allocate leak
If a cache entry permission was previously set to NotPresent, but the entry was
not deleted, a following cache allocation can cause the entry to be leaked by
setting the entry pointer to a newly allocated entry. To eliminate this
possibility, check if the new entry is different from the old one, and if so,
delete the old one.
2015-09-29 09:28:26 -05:00
Joel Hestness
0ecaab4ea8 arch, x86: Delete packet in IntDevice::recvResponse
IntDevice::recvResponse is called from two places in current mainline: (1) the
short circuit path of X86ISA::IntDevice::IntMasterPort::sendMessage for atomic
mode, and (2) the full request->response path to and from the x86 interrupts
device (finally called from MessageMasterPort::recvTimingResp). In the former
case, the packet was deleted correctly, but in the latter case, the packet and
request leak. To fix the leak, move request and packet deletion into IntDevice
inherited class implementations of recvResponse.
2015-09-29 09:28:26 -05:00
Joel Hestness
b80024ee7d ruby: RubyPort delete snoop requests
In RubyPort::ruby_eviction_callback, prior changes fixed a memory leak caused
by instantiating separate packets for each port that the eviction was forwarded
to. That change, however, left the instantiated request to also leak. Allocate
it on the stack to avoid the leak.
2015-09-29 09:28:25 -05:00
Joel Hestness
7b70fa02ae ruby: Fix memory leak in AbstractController
Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.
2015-09-29 09:28:25 -05:00
Joel Hestness
501705eaf0 ruby: RubyMemoryControl delete requests
Changes to the RubyMemoryControl removed the dequeue function, which deleted
MemoryNode instances. This results in leaked MemoryNode instances. Correctly
delete these instances.
2015-09-29 09:25:29 -05:00
Joel Hestness
395b31f518 syscall_emul: Bandage readlink /proc/self/exe
The recent changeset to readlink() to handle reading the /proc/self/exe link
introduces a number of problems. This patch fixes two:

1) Because readlink() called on /proc/self/exe now uses LiveProcess::progName()
to find the binary path, it will only get the zeroth parameter of the simulated
system command line. However, if a config script also specifies the process'
executable, the executable parameter is used to create the LiveProcess rather
than the zeroth command line parameter. Thus, the zeroth command line parameter
is not necessarily the correct path to the binary executing in the simulated
system. To fix this, add a LiveProcess data member, 'executable', which is
correctly set during instantiation and returned from progName().

2) If a config script allows a user to pass a relative path as the zeroth
simulated system command line parameter or process executable, readlink() will
incorrecly return a relative path when called on '/proc/self/exe'.
/proc/self/exe is always set to a full path, so running benchmarks can fail if
a relative path is returned. To fix this, clean up the handling of
LiveProcess::progName() within readlink() to get the full binary path.

NOTE: This patch still leaves the potential problem that host full path to the
binary bleeds into the simulated system, potentially causing the appearance of
non-deterministic simulated system execution.
2015-09-29 09:25:20 -05:00
Andreas Hansson
9a0129dcbf mem: Add PacketInfo to be used for packet probe points
This patch fixes a use-after-delete issue in the packet probe points
by adding a PacketInfo struct to retain the key fields before passing
the packet onwards. We want to probe the packet after it is
successfully sent, but by that time the fields may be modified, and
the packet may even be deleted.

Amazingly enough the issue has gone undetected for months, and only
recently popped up in our regressions.
2015-09-25 13:25:34 -04:00
Andreas Hansson
806e1fbf0f stats: Update stats to reflect snoop-filter changes 2015-09-25 07:27:03 -04:00
Andreas Hansson
a9a7002a3b mem: Add check for block status on WriteLineReq fill
More checks to help with understanding of functionality.
2015-09-25 07:26:58 -04:00
Andreas Hansson
012dd52dc2 mem: Fix WriteLineReq fill behaviour
This patch fixes issues in the interactions between deferred snoops
and WriteLineReq. More specifically, the patch addresses an issue
where deferred snoops caused assertion failures when being serviced on
the arrival of an InvalidateResp. The response packet was perceived to
be invalidating, when actually it is not for the cache that sent out
the original invalidation request.
2015-09-25 07:26:58 -04:00
Andreas Hansson
5570aa9e9a mem: Comment clean-up for the snoop filter
Merely fixing up some style issues and adding more comments.
2015-09-25 07:26:57 -04:00
Andreas Hansson
7d4e89d4e0 mem: Avoid adding and then removing empty snoop-filter items
This patch tidies up how we access the snoop filter for snoops, and
avoids adding items only to later remove them.
2015-09-25 07:26:57 -04:00
Andreas Hansson
ca163a80e2 mem: Only track snooping ports in the snoop filter
This patch changes the tracking of ports in the snoop filter to use
local dense port IDs so that we can have 64 snooping ports (rather
than crossbar slave ports). This is achieved by adding a simple
remapping vector that translates the actal port IDs into the local
slave IDs used in the SnoopMask.

Ultimately this patch allows us to scale to much larger systems
without introducing a hierarchy of crossbars.
2015-09-25 07:26:57 -04:00
Ali Jafri
3aa87251d7 mem: Add snoop filters to L2 crossbars, and check size
This patch adds a snoop filter to the L2XBar. For now we refrain from
globally adding a snoop filter to the SystemXBar, since the latter is
also used in systems without caches. In scenarios without caches the
snoop filter will not see any writeback/clean evicts from the CPU
ports, despite the fact that they are snooping. To avoid inadvertent
use of the snoop filter in these cases we leave it out for now.

A size check is added to the snoop filter, merely to ensure it does
not grow beyond the total capacity of the caches above it. The size
has to be set manually, and a value of 8 MByte is choosen as suitably
high default.
2015-09-25 07:26:57 -04:00
Andreas Hansson
0c5a98f9d1 mem: Store snoop filter lookup result to avoid second lookup
This patch introduces a private member storing the iterator from the
lookupRequest call, such that it can be re-used when the request
eventually finishes. The method previously called updateRequest is
renamed finishRequest to make it more clear that the two functions
must be called together.
2015-09-25 07:26:57 -04:00
Ali Jafri
ceec2bb02c mem: Add snoops for CleanEvicts and Writebacks in atomic mode
This patch mirrors the logic in timing mode which sends up snoops to
check for cached copies before sending CleanEvicts and Writebacks down
the memory hierarchy. In case there is a copy in a cache above,
discard CleanEvicts and set the BLOCK_CACHED flag in Writebacks so
that writebacks do not reset the cache residency bit in the snoop
filter below.
2015-09-25 07:26:57 -04:00
Ali Jafri
6ac356f93b mem: Add CleanEvict and Writeback support to snoop filters
This patch adds the functionality to properly track CleanEvicts and
Writebacks in the snoop filter. Previously there were no CleanEvicts, and
Writebacks did not send up snoops to ensure there were no copies in
caches above. Hence a writeback could never erase an entry from the
snoop filter.

When a CleanEvict message reaches a snoop filter, it confirms that the
BLOCK_CACHED flag is not set and resets the bits corresponding to the
CleanEvict address and port it arrived on. If none of the other peer
caches have (or have requested) the block, the snoop filter forwards
the CleanEvict to lower levels of memory. In case of a Writeback
message, the snoop filter checks if the BLOCK_CACHED flag is not set
and only then resets the bits corresponding to the Writeback
address. If any of the other peer caches have (or has requested) the
same block, the snoop filter sets the BLOCK_CACHED flag in the
Writeback before forwarding it to lower levels of memory heirarachy.
2015-09-25 07:26:57 -04:00
Ali Jafri
79d3dbcea8 mem: Add check for snooping ports in the snoop filter
This patch prevents the snoop filter from creating items for requests
originating from non-snooping ports. The allocation decision is thus
based both on the cacheability of the line, and the snooping status of
the source port. Ultimately we should check if the source of the
packet is caching, since also the CPU ports are snooping (but not
allocating). Thus, at the moment we rely on the snoop filter being
used together with caches.

The patch also transitions to use the Packet::getBlockAddr in
determining the line address.
2015-09-25 07:26:57 -04:00
Andreas Hansson
462c288a75 mem: Make the coherent crossbar account for timing snoops
This patch introduces the concept of a snoop latency. Given the
requirement to snoop and forward packets in zero time (due to the
coherency mechanism), the latency is accounted for later.

On a snoop, we establish the latency, and later add it to the header
delay of the packet. To allow multiple caches to contribute to the
snoop latency, we use a separate variable in the packet, and then take
the maximum before adding it to the header delay.
2015-09-25 07:13:54 -04:00
Andreas Hansson
3bd78a141e mem: Do not include snoop-filter latency in crossbar occupancy
This patch ensures that the snoop-filter latency only contributes to
the packet latency, and not to the crossbar throughput/occupancy. In
essence we treat the snoop-filter lookup as pipelined.
2015-09-25 06:45:52 -04:00
Andreas Hansson
40fcb59c54 util: Fix minor issues in DRAM sweep scripts
This patch fixes a few issues in the sweep scripts, bringing them
up-to-date with the latest memory configs and options.
2015-09-25 06:45:50 -04:00
Nilay Vaish
4647e4e961 ruby: simple network: refactor code
Drops an unused variable and marks three variables as const.
2015-09-24 08:41:24 -05:00
Nilay Vaish
b3a3b0b6cf ruby: garnet: refactor code in network links 2015-09-23 11:23:11 -05:00
Nilay Vaish
6bd7aa1f20 ruby: bloom filters: refactor code 2015-09-23 11:23:10 -05:00
Nilay Vaish
c2376918a5 ruby: abstract controller: mark some variables as const 2015-09-23 11:23:10 -05:00
Wendy Elsasser
61c38524ce mem: Add initial HBM configurations
Created the following HBM configurations:
1) HBM gen1 (x128/CH), 2Gb die, 4H stack, 1Gbps, 8 channels
2) HBM gen2 (x64/PC), 8Gb die, 4H stack, 1Gbps, 16 pseudo-channels

The configuration values are based on:
- The HBM gen1 public JEDEC spec
- Publically released data from MemCon presentations
- Timing extrapolated from existing LPDDR configurations

Will adjust once specs become available.
2015-09-22 13:17:53 -05:00