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11304 commits

Author SHA1 Message Date
Steve Reinhardt
1b6355c895 cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.

This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.

This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().

For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level.  For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.
2016-01-17 18:27:46 -08:00
Steve Reinhardt
707275265f cpu: remove unnecessary data ptr from O3 internal read() funcs
The read() function merely initiates a memory read operation; the
data doesn't arrive until the access completes and a response packet
is received from the memory system.  Thus there's no need to provide
a data pointer; its existence is historical.

Getting this pointer out of this internal o3 interface sets the
stage for similar cleanup in the ExecContext interface.  Also
found that we were pointlessly setting the contents at this pointer
on a store forward (the useful memcpy happens just a few lines
below the deleted one).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
e595d9cccb arch: don't call *Timing functions from *Atomic versions
The readMemAtomic/writeMemAtomic helper functions were calling
readMemTiming/writeMemTiming respectively.  This is functionally
correct, since the *Timing functions are doing the same access
initiation operation as the *Atomic functions (just that the
*Atomic versions also complete the access in line).  It also
provides for some (very minimal) code reuse.  Unfortunately,
it's potentially pretty confusing, since it makes it look like
the atomic accesses are somehow being converted to timing
accesses.  It also gets in the way of specializing the timing
interface (as will be done in a future patch).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
fb0383bc72 arch: get rid of unused LargestRead typedef 2016-01-17 18:27:46 -08:00
Steve Reinhardt
28a0e5a165 sim: don't ignore SIG_TRAP
By ignoring SIG_TRAP, using --debug-break <N> when not connected to
a debugger becomes a no-op.  Apparently this was intended to be a
feature, though the rationale is not clear.

If we don't ignore SIG_TRAP, then using --debug-break <N> when not
connected to a debugger causes the simulation process to terminate
at tick N.  This is occasionally useful, e.g., if you just want to
collect a trace for a specific window of execution then you can combine
this with --debug-start to do exactly that.

In addition to not ignoring the signal, this patch also updates
the --debug-break help message and deletes a handful of unprotected
calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-17 18:27:46 -08:00
Steve Reinhardt
fcfe6e798d stats: update SPARC FS stats
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was
broken for so long that, now that it's working again, the stats
output is out of date.  This changeset updates the outputs, on
the assumption that the stats changes are all valid differences
due to other changes made while it was broken.
2016-01-17 21:13:29 -05:00
Andreas Sandberg
745f8229f6 dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:

  * Automatic PCI interrupt assignment
  * PCI interrupts allocated in a contiguous range.
  * Automatic boot loader selection (32-bit / 64-bit)
  * Cleaner memory map where gem5-specific devices live in CS5 which
    isn't used by current Versatile Express platforms.
  * No fake devices. Devices that were previously faked will be
    removed from the device tree instead.
  * Support for 510 GiB contiguous memory
2016-01-15 11:30:13 +00:00
Andreas Sandberg
6d058a63b0 dev, arm: Add support for automatic PCI interrupt routing
Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.

Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:

  * ARM_PCI_INT_STATIC: Use the old static routing policy using the
    interrupt line from a device's configurtion space.

  * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
    interrupt in the GIC. The interrupt is computed as:

    gic_int = int_base + (pci_dev % int_count)

  * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
    an interrupt in the GIC. The PCI specification reserves pin ID 0
    for devices without interrupts, the interrupt therefore computed
    as:

    gic_int = int_base + ((pin - 1) % int_count)
2016-01-15 11:30:06 +00:00
Steve Reinhardt
8406a54907 mem: fix bug in packet access endianness changes
The new Packet::setRaw() method incorrectly still contained
an htog() conversion.  As a result, calls to the old set()
method (now defined as setRaw(htog(v))) underwent two htog
conversions, which breaks things when htog() is not a no-op.

Interestingly the only test that caught this was a SPARC
boot test, where an IsaFake device with a non-zero return
value was getting swapped twice resulting in a register
getting loaded with 0x100000000000000 instead of 1.
(Good reason for keeping SPARC around, perhaps?)
2016-01-11 16:20:38 -05:00
Andreas Hansson
12eb034378 scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
2016-01-11 05:52:20 -05:00
Andreas Hansson
7661f1c2bf ext: Replace gzstream with iostream3 from zlib to avoid LGPL
This patch replaces the gzstream zlib wrapper with the iostream3
wrapper provided as part of zlib contributions. The main reason for
the switch is to avoid including LGPL in the default gem5
build. iostream3 is provided under a more permissive license:

The code is provided "as is", with the permission to use, copy,
modify, distribute and sell it for any purpose without fee.
2016-01-11 05:52:18 -05:00
Andreas Hansson
c965ca96cc configs: Fix inheritance of HMCSystem and cleanup spacing
Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.
2016-01-11 05:52:17 -05:00
Gabor Dozsa
64ca31976f config: Updates for distributed gem5 simulations 2016-01-07 16:33:47 -06:00
Gabor Dozsa
5dec4e07b8 dev: Distributed Ethernet link for distributed gem5 simulations
Distributed gem5 (abbreviated dist-gem5) is the result of the
convergence effort between multi-gem5 and pd-gem5 (from Univ. of
Wisconsin). It relies on the base multi-gem5 infrastructure for packet
forwarding, synchronisation and checkpointing but combines those with
the elaborated network switch model from pd-gem5.

--HG--
rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc
rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh
rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc
rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh
rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2016-01-07 16:33:47 -06:00
Gabor Dozsa
e677494260 pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from
within the simulated software.
2016-01-07 16:33:47 -06:00
Steve Reinhardt
6caa2c9b4e mem: add CacheVerbose debug flag, filter noisy DPRINTFs
Some of the DPRINTFs added to the classic cache in cset 45df88079f04,
while useful to those unfamiliar with the cache code, end up being
noise when you're familiar with the code but are trying to debug tricky
protocol issues.  (Particularly getting two messages from each cache
as it receives a snoop request then declares that there was no match.)

This patch introduces a CacheVerbose debug flag, and moves a subset of
the added DPRINTFs into that category, so that Cache by itself returns
to being a more succinct summary of cache activity.

Also added a CacheAll compound flag to turn on all the cache-related
debug flags (other than CacheTags, which you *really* have to want badly
to turn it on, IMO).
2015-12-31 09:32:09 -08:00
Andreas Hansson
c153b669fd mem: Do not rely on the NeedsWritable flag for responses
This patch removes the NeedsWritable flag for all responses, as it is
really only the request that needs a writable response. The response,
on the other hand, should in these cases always provide the line in a
writable state, as indicated by the hasSharers flag not being set.

When we send requests that has NeedsWritable set, the response will
always have the hasSharers flag not set. Additionally, there are cases
where the request did not have NeedsWritable set, and we still get a
writable response with the hasSharers flag not set. This never happens
on snoops, but is used by downstream caches to pass ownership
upstream.

As part of this patch, the affected response types are updated, and
the snoop filter is similarly modified to check only the hasSharers
flag (as it should). A sanity check is also added to the packet class,
asserting that we never look at the NeedsWritable flag for responses.

No regressions are affected.
2015-12-31 09:34:18 -05:00
Andreas Hansson
7fca994d04 mem: Do not allocate space for packet data if not needed
This patch looks at the request and response command to determine if
either actually has any data payload, and if not, we do not allocate
any space for packet data.

The only tricky case is where the command type is changed as part of
the MSHR functionality. In these cases where the original packet had
no data, but the new packet does, we need to explicitly call
allocate().
2015-12-31 09:33:39 -05:00
Andreas Hansson
f1ec326be5 mem: Do not alter cache block state on uncacheable snoops
This patch ensures we do not respond with a Modified (dirty and
writable) line if the request is uncacheable, and that the cache
responding retains the line without modifying the state (even if
responding).
2015-12-31 09:33:25 -05:00
Andreas Hansson
0fcb376e5f mem: Make cache terminology easier to understand
This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
2015-12-31 09:32:58 -05:00
Tony Gutierrez
a317764577 ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one.  The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier.  This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
2015-07-20 09:15:18 -05:00
Tony Gutierrez
3f68884c0e ruby: slicc: remove support for single machine, multiple types
This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.
2015-07-20 09:15:18 -05:00
Steve Reinhardt
3840a72f37 stats: more updates due to PCI changes
A couple of the long regressions have been showing as CHANGED
since 11244:a2af58a06c4e despite the updates in 11245:1c5102c0a7a9.
The x86 regression looks like it was just missed, but it's not clear
why the ARM one is giving different results (perhaps a non-determinism
between zizzer and wherever the updated results were run?).
2015-12-30 11:18:44 -05:00
Steve Reinhardt
2b49d3b6ca tests: update EIO reference outputs 2015-12-28 15:43:06 -05:00
Andreas Hansson
f5c4a45889 mem: Explicitly check MSHR snoops for cases not dealt with
Add a sanity check to make it explicit that we currently do not allow
an I/O coherent agent to directly issue writes into the coherent part
of the memory system (it has to go via a cache, and get transformed
into a read ex, upgrade or invalidation).
2015-12-28 11:14:18 -05:00
Andreas Hansson
f6525ff221 mem: Remove unused cache squash functionality
This patch removes the unused squash function from the MSHR queue, and
the associated (and also unused) threadNum member from the MSHR.
2015-12-28 11:14:16 -05:00
Andreas Hansson
fbf3987c7b mem: Avoid unecessary checks when creating HardPFReq in cache
The checks made before sending out a HardPFReq were unecessarily
complex, and checked for cases that never occur. This patch
tidies it up.
2015-12-28 11:14:15 -05:00
Andreas Hansson
b93a9d0d51 mem: Do not use sender state to track forwarded snoops in cache
This patch changes how the cache tracks which snoops are forwarded,
and which ones are created locally. Previously the identification was
based on an empty sender state of a specific class, but this method
fails to distinguish which cache actually attached the sender
state. Instead we use the same mechanism as the crossbar, and keep
track of the requests that have outstanding snoops.
2015-12-28 11:14:14 -05:00
Andreas Hansson
036263e280 mem: Fix cache sender state handling and add clarification
This patch addresses a bug in how the cache attached the MSHR as a
sender state. Rather than overwriting any existing sender state it now
pushes a new one. The handling of upward snoops is also clarified.
2015-12-28 11:14:10 -05:00
Boris Shingarov
d765dbf22c arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays.  The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question.  This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).

With this patch I propose a simpler mechanism for expressing the
register set structure.  In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation.  The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.

This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.

Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 15:12:07 -06:00
Andreas Sandberg
b5a54eb64e sim: Use the old work item behavior by default
When adding an option to forward work items to the Python environment,
the new behavior was accidentally enabled by default. Set the value of
exit_on_work_items to False by default to revert to the old behavior
unless the simulation scripts explicitly requests work item
forwarding.
2015-12-18 10:14:17 +00:00
Andreas Hansson
219f1c1a7f configs: Make the default memtest behaviour more complex
Add functional and uncacheable accesses by default.
2015-12-17 17:07:22 -05:00
Andreas Hansson
97887eb6dc mem: Fix memory allocation bug in deferred snoop handling
This patch fixes a corner case in the deferred snoop handling, where
requests ended up being used by multiple packets with different
lifetimes, and inadvertently got deleted while they were still in use.
2015-12-17 17:07:11 -05:00
Andreas Sandberg
08754488a3 sim: Add an option to forward work items to Python
There are cases where we want the Python world to handle work items
instead of the C++ world. However, that's currently not possible. This
changeset adds the forward_work_items option to the System class. Then
it is set to True, work items will generate workbegin/workend
simulation exists with the work item ID as the exit code and the old
C++ handling is completely bypassed.

--HG--
extra : rebase_source : 8de637a744fc4b6ff2bc763f00cdf8ddf2bff885
2015-12-14 17:10:36 +00:00
David Hashe
f5f04c3120 mem: add request types for acquire and release
Add support for acquire and release requests.  These synchronization operations
are commonly supported by several modern instruction sets.
2015-07-20 09:15:18 -05:00
Anthony Gutierrez
4935f0d5ff stats: bump stats to reflect ruby tester changes 2015-12-12 17:27:38 -05:00
Brad Beckmann
634f34d3f2 regress: updates required for the compute-gpu patches 2015-12-11 16:07:01 -05:00
Brad Beckmann
173a786921 ruby: more flexible ruby tester support
This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests.  This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code.  Finally, the patch also includes better DPRINTFs for
debugging the tester.
2015-07-20 09:15:18 -05:00
Andreas Sandberg
4e6241007c dev: Add missing SConscript in src/dev/i2c 2015-12-10 18:46:02 +00:00
Andreas Sandberg
8ec5fc6632 dev: Move storage devices to src/dev/storage/
Move the IDE controller and the disk implementations to
src/dev/storage.

--HG--
rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py
rename : src/dev/Ide.py => src/dev/storage/Ide.py
rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py
rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc
rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh
rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h
rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc
rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh
rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc
rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh
rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h
rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc
rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh
2015-12-10 10:35:23 +00:00
Andreas Sandberg
23c961a0fd dev: Move network devices to src/dev/net/
--HG--
rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py
rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc
rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh
rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc
rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh
rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc
rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh
rename : src/dev/etherint.cc => src/dev/net/etherint.cc
rename : src/dev/etherint.hh => src/dev/net/etherint.hh
rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc
rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh
rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh
rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc
rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh
rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc
rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh
rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc
rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh
rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh
rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc
rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh
rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc
rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh
rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc
rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh
rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc
rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh
rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h
rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc
rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh
rename : src/dev/sinic.cc => src/dev/net/sinic.cc
rename : src/dev/sinic.hh => src/dev/net/sinic.hh
rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh
rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc
rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
2015-12-10 10:35:18 +00:00
Andreas Sandberg
ef097ac438 dev: Move i2c functionality to src/dev/i2c/
--HG--
rename : src/dev/I2C.py => src/dev/i2c/I2C.py
rename : src/dev/i2cbus.cc => src/dev/i2c/bus.cc
rename : src/dev/i2cbus.hh => src/dev/i2c/bus.hh
rename : src/dev/i2cdev.hh => src/dev/i2c/device.hh
2015-12-10 10:35:18 +00:00
Andreas Sandberg
38e2860c36 dev: Move the CopyEngine class to src/dev/pci
--HG--
rename : src/dev/CopyEngine.py => src/dev/pci/CopyEngine.py
rename : src/dev/copy_engine.cc => src/dev/pci/copy_engine.cc
rename : src/dev/copy_engine.hh => src/dev/pci/copy_engine.hh
rename : src/dev/copy_engine_defs.hh => src/dev/pci/copy_engine_defs.hh
2015-12-10 10:35:16 +00:00
Andreas Sandberg
139c97c977 dev: Move existing PCI device functionality to src/dev/pci
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.

--HG--
rename : src/dev/Pci.py => src/dev/pci/PciDevice.py
rename : src/dev/pcidev.cc => src/dev/pci/device.cc
rename : src/dev/pcidev.hh => src/dev/pci/device.hh
rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
2015-12-10 10:35:15 +00:00
Sascha Bischoff
2d79bf3d4d sim: Disable gzip compression for writefile pseudo instruction
The writefile pseudo instruction uses OutputDirectory::create and
OutputDirectory::openFile to create the output files. However, by
default these will check the file extention for .gz, and create a gzip
compressed stream if the file ending matches. When writing out files,
we want to write them out exactly as they are in the guest simulation,
and never want to compress them with gzio. Additionally, this causes
m5 writefile to fail when checking the error flags for the output
steam.

With this patch we add an additional no_gz argument to
OutputDirectory::create and OutputDirectory::openFile which allows us
to override the gzip compression.  Therefore, for m5 writefile we
disable the filename check, and always create a standard ostream.
2015-11-05 18:26:23 +00:00
Karthik Sangaiah
47326f5422 arm: Bootloader fix for v8 over 16 cores
Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
2015-07-15 14:43:35 +01:00
Karthik Sangaiah
6fa936b021 dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.

When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.

This changeset is based on previous work by Matt Evans.
2015-09-18 16:49:28 +01:00
Tony Gutierrez
413f3088ea mem: remove acq/rel cmds from packet and add mem fence req 2015-12-09 22:56:31 -05:00
Steve Reinhardt
28d7e261ed syscall_emul: don't check host fd when allocating target fd
There's a well-meaning check in Process::allocFD() to return an invalid
target fd (-1) if the incoming host fd is -1.  However, this means that
emulated drivers, which want to allocate a target fd that doesn't
correspond to a host fd, can't use -1 to indicate an intentionally
invalid host fd.

It turns out the allocFD() check is redundant, as callers always test
the host fd for validity before calling.  Also, callers never test the
return value of allocFD() for validity, so even if the test failed,
it would likely have the undesirable result of returning -1 to the
target app as a file descriptor without setting errno.

Thus the check is pointless and is now getting in the way, so it seems
we should just get rid of it.
2015-12-09 14:47:43 -05:00
Curtis Dunham
7c4a6604b9 ext: fix SST connector
Writeback no longer a MemCmd.
2015-12-08 14:30:31 -06:00