Commit graph

7869 commits

Author SHA1 Message Date
Gabe Black
7378424b14 X86: Make syscalls also serialize after. 2010-10-29 02:20:46 -07:00
Gabe Black
d5dbd91f3d O3: Get rid of a bunch of commented out lines. 2010-10-24 00:43:32 -07:00
Gabe Black
df3fd79d1f Configs: Stop setting the "mem" parameter in splash2 config files.
This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
2010-10-22 20:59:22 -07:00
Gabe Black
2eae11be64 X86: Make nop a regular, non-microcoded instruction.
Code in the CPUs that need a nop to carry a fault can't easily deal with a
microcoded nop. This instruction format provides for one that isn't.

--HG--
rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
2010-10-22 00:24:15 -07:00
Gabe Black
23f6196d61 X86: Implement genMachineCheckFault.
Even though this shouldn't ever be used, it might get called speculatively and
shouldn't panic.
2010-10-22 00:24:08 -07:00
Gabe Black
255685534a X86: Make syscall instructions non-speculative in SE. 2010-10-22 00:23:50 -07:00
Gabe Black
29676286c8 ISA: Simplify various implementations of completeAcc. 2010-10-22 00:23:19 -07:00
Gabe Black
bc49381287 ARM: Don't pretend to writeback registers in initiateAcc. 2010-10-22 00:22:59 -07:00
Steve Reinhardt
45aebaccde cache: minor SC assertion fix
Thanks to Joe Gross for finding/testing this.
2010-10-18 13:05:15 -07:00
Gabe Black
968447db66 MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha. 2010-10-17 23:15:53 -07:00
Gabe Black
b289966a78 Mem: Reclaim some request flags used by MIPS for alignment checking.
These flags were being used to identify what alignment a request needed, but
the same information is available using the request size. This change also
eliminates the isMisaligned function. If more complicated alignment checks are
needed, they can be signaled using the ASI_BITS space in the flags vector like
is currently done with ARM.
2010-10-16 00:00:54 -07:00
Gabe Black
ab9f062166 GetArgument: Rework getArgument so that X86_FS compiles again.
When no size is specified for an argument, push the decision about what size
to use into the ISA by passing a size of -1.
2010-10-15 23:57:06 -07:00
Gabe Black
b197a542b4 SPARC: Get rid of the copy/pasted StackTrace stolen from Alpha. 2010-10-14 14:02:23 -07:00
Gabe Black
930c653270 Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-10-13 01:57:31 -07:00
Gabe Black
b273e0be33 X86: Detect attempts to load a 32 bit kernel and panic. 2010-10-10 20:39:26 -07:00
Gabe Black
157d6f9c2f SPARC: Make SPARC's ISA's clear function initialize everything it should.
Also make it not set some pointers to NULL potentially introducing a memory
leak. That should be done in the constructor.
2010-10-10 20:38:05 -07:00
Gabe Black
63fa65613e Alpha: Force all the IPRs to an initial, determinstic value when cleared. 2010-10-10 20:37:50 -07:00
Gabe Black
b4a76f0b0b Alpha: Initialize the data TLB mode IPR. 2010-10-10 20:37:39 -07:00
Gabe Black
9268f895d5 UART: Make the 8250's MCR return a deterministic value.
This change makes the 8250 device return the value it has for the MCR when
read instead of leaving the packet data unmodified/uninitialized. The value
the UART has for the MCR may not be right, but that's a seperate issue that
apparently hasn't caused any problems to date.
2010-10-09 12:41:31 -07:00
Gabe Black
d4492190e6 Alpha: Fix Alpha NumMiscArchRegs constant.
Also add asserts in O3's Scoreboard class to catch bad indexes.
2010-10-04 11:58:06 -07:00
Ali Saidi
538acf2082 Power: Fix compile error from previous push. 2010-10-01 17:57:56 -05:00
Ali Saidi
dcaa0668ae ARM: Make the TLB a little bit faster by moving most recently used items to front of list 2010-10-01 16:04:04 -05:00
Ali Saidi
f0c0b8a7f6 ARM: Add a fake flash controller so that unmodified linux can boot
With this change an unmodified Linux kernel can boot in M5.
2010-10-01 16:04:02 -05:00
Prakash Ramrakhyani
9792bbc324 ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte
accesses which could set/clear different numbers of interrupts.
2010-10-01 16:04:00 -05:00
Ali Saidi
521d68c82a ARM: Implement functional virtual to physical address translation
for debugging and program introspection.
2010-10-01 16:03:27 -05:00
Ali Saidi
518b5e5b1c Debug: Implement getArgument() and function skipping for ARM.
In the process make add skipFuction() to handle isa specific function skipping
instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can
only start in even registers.  Size is now passed to getArgument() so that 32
bit systems can make decisions about register selection for 64 bit arguments.
The number argument is now passed by reference because getArgument() will need
to change it based on the size of the argument and the current argument number.

For ARM, if the argument number is odd and a 64-bit register is requested the
number must first be incremented to because all 64 bit arguments are passed
in an even argument register. Then the number will be incremented again to
access both halves of the argument.
2010-10-01 16:02:46 -05:00
Ali Saidi
b331b02669 ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.
2010-10-01 16:02:45 -05:00
Ali Saidi
aef4a9904e CPU/Cache: Fix some errors exposed by valgrind 2010-09-30 09:35:19 -05:00
Gabe Black
c41e633e0e X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions. 2010-09-29 11:31:03 -07:00
Steve Reinhardt
7bae1f5d43 python: get rid of internal.enums package.
Move generated enums into internal.params, which gets
imported into object.params, restoring backward
compatibility for scripts that expect to find them there.
2010-09-22 08:45:35 -07:00
Steve Reinhardt
13a15c55a4 stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt
e918536380 cache: improve coherence handling of writebacks
If we write back an exclusive copy, we now mark it
as such, so the cache receiving the writeback can
mark its copy as exclusive.  This avoids some
unnecessary upgrade requests when a cache later
tries to re-acquire exclusive access to the block.
2010-09-21 23:07:34 -07:00
Steve Reinhardt
0bd9cea340 diff-out: clean up options
Make diff-out sort stats changes by percentage
by default, with '-a' to use current alpha sort
(instead of requiring '-p' to sort by percentage).
Other minor options cleanup too.
2010-09-21 23:07:34 -07:00
Steve Reinhardt
db2f226834 tests: print if output files match
Add '-s' flag to diff command generating outdiff
file so we have positive confirmation when
outputs match.
2010-09-21 23:07:34 -07:00
Gabe Black
ab8d7eee76 CPU: Fix O3 and possible InOrder segfaults in FS. 2010-09-20 02:46:42 -07:00
Steve Reinhardt
3f9f4bf3d6 devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore.  Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
2010-09-16 20:24:05 -07:00
Gabe Black
2dd9f4fcf0 X86: Make the halt microop non-speculative.
Executing this microop makes the CPU halt even if it was misspeculated.
2010-09-14 12:31:37 -07:00
Gabe Black
0bbd88eb40 X86: Make unrecognized instructions behave better in x86. 2010-09-14 12:27:30 -07:00
Gabe Black
0dd1f7f01a CPU: Trim unnecessary includes from some common files.
This reduces the scope of those includes and makes it less likely for there to
be a dependency loop. This also moves the hashing functions associated with
ExtMachInst objects to be with the ExtMachInst definitions and out of
utility.hh.
2010-09-14 00:29:38 -07:00
Gabe Black
8f3fbd2d13 CPU: Get rid of the now unnecessary getInst/setInst family of functions.
This code is no longer needed because of the preceeding change which adds a
StaticInstPtr parameter to the fault's invoke method, obviating the only use
for this pair of functions.
2010-09-13 21:58:34 -07:00
Gabe Black
6833ca7eed Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
2010-09-13 19:26:03 -07:00
Nathan Binkert
2edfcbbaee swig: make all generated files go into the m5.internal package
This is necessary because versions of swig older than 1.3.39 fail to
do the right thing and try to do relative imports for everything (even
with the package= option to %module).  Instead of putting params in
the m5.internal.params package, put params in the m5.internal package
and make all param modules start with param_.  Same thing for
m5.internal.enums.

Also, stop importing all generated params into m5.objects.  They are
not necessary and now with everything using relative imports we wound
up with pollution of the namespace (where builtin-range got overridden).

--HG--
rename : src/python/m5/internal/enums/__init__.py => src/python/m5/internal/enums.py
rename : src/python/m5/internal/params/__init__.py => src/python/m5/internal/params.py
2010-09-12 15:41:34 -07:00
Nathan Binkert
afafaf1dcb style: fix sorting of includes and whitespace in some files 2010-09-10 14:58:04 -07:00
Nathan Binkert
47ef97b9ca scons: Stop building the big monolithic swigged params module
kill params.i and create a separate .i for each object (param, enums, etc.)
2010-09-09 14:26:29 -07:00
Nathan Binkert
e6ee56c657 init: don't build files that centralize python and swig code
Instead of putting all object files into m5/object/__init__.py, interrogate
the importer to find out what should be imported.
Instead of creating a single file that lists all of the embedded python
modules, use static object construction to put those objects onto a list.
Do something similar for embedded swig (C++) code.
2010-09-09 14:15:42 -07:00
Nathan Binkert
710ed8f492 scons: use code_formatter wherever we can in the build system 2010-09-09 14:15:41 -07:00
Nathan Binkert
c514ad9b09 code_formatter: make it easier to insert whitespace
a newline by just doing "code()". indent() and dedent() now take a
"count" parameter to indent/dedent multiple levels.
2010-09-09 14:15:41 -07:00
Nathan Binkert
18ef1bcfa2 swig: don't override SWIG_name anymore
It doesn't appear to be necessary and it is somewhat odd.  I'm pretty
sure that the package parameter to %module does whatever this might
have been before.  It's necessary in future revisions anyway.
2010-09-09 14:15:40 -07:00
Steve Reinhardt
9e45ada171 stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
1249728494 cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f.  The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache.  To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
2010-09-09 14:40:19 -04:00