CPU: Trim unnecessary includes from some common files.

This reduces the scope of those includes and makes it less likely for there to
be a dependency loop. This also moves the hashing functions associated with
ExtMachInst objects to be with the ExtMachInst definitions and out of
utility.hh.

src/arch/alpha/isa.cc

@@ -33,6 +33,7 @@
 #include "arch/alpha/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
+#include "sim/serialize.hh"
 
 namespace AlphaISA
 {

src/arch/arm/types.hh

@@ -44,6 +44,7 @@
 #define __ARCH_ARM_TYPES_HH__
 
 #include "base/bitunion.hh"
+#include "base/hashmap.hh"
 #include "base/types.hh"
 
 namespace ArmISA
@@ -269,4 +270,13 @@ namespace ArmISA
 
 } // namespace ArmISA
 
+namespace __hash_namespace {
+    template<>
+    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
+        size_t operator()(const ArmISA::ExtMachInst &emi) const {
+            return hash<uint32_t>::operator()((uint32_t)emi);
+        };
+    };
+}
+
 #endif

src/arch/arm/utility.hh

@@ -47,21 +47,11 @@
 
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
-#include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"
 
-namespace __hash_namespace {
-    template<>
-    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
-        size_t operator()(const ArmISA::ExtMachInst &emi) const {
-            return hash<uint32_t>::operator()((uint32_t)emi);
-        };
-    };
-}
-
 namespace ArmISA {
 
     inline bool

src/arch/power/insts/branch.cc

@@ -30,6 +30,7 @@
 
 #include "arch/power/insts/branch.hh"
 #include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
 
 using namespace PowerISA;
 

src/arch/power/types.hh

@@ -32,6 +32,7 @@
 #define __ARCH_POWER_TYPES_HH__
 
 #include "base/bitunion.hh"
+#include "base/hashmap.hh"
 #include "base/types.hh"
 
 namespace PowerISA
@@ -88,4 +89,15 @@ struct CoreSpecific {
 
 } // PowerISA namspace
 
+namespace __hash_namespace {
+
+template<>
+struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
+    size_t operator()(const PowerISA::ExtMachInst &emi) const {
+        return hash<uint32_t>::operator()((uint32_t)emi);
+    };
+};
+
+} // __hash_namespace namespace
+
 #endif // __ARCH_POWER_TYPES_HH__

src/arch/power/utility.hh

@@ -35,23 +35,9 @@
 #ifndef __ARCH_POWER_UTILITY_HH__
 #define __ARCH_POWER_UTILITY_HH__
 
-#include "arch/power/miscregs.hh"
-#include "arch/power/types.hh"
-#include "base/hashmap.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"
 
-namespace __hash_namespace {
-
-template<>
-struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
-    size_t operator()(const PowerISA::ExtMachInst &emi) const {
-        return hash<uint32_t>::operator()((uint32_t)emi);
-    };
-};
-
-} // __hash_namespace namespace
-
 namespace PowerISA {
 
 /**

src/arch/x86/types.hh

@@ -44,6 +44,7 @@
 
 #include "base/bitunion.hh"
 #include "base/cprintf.hh"
+#include "base/hashmap.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
@@ -225,6 +226,26 @@ namespace X86ISA
     };
 };
 
+namespace __hash_namespace {
+    template<>
+    struct hash<X86ISA::ExtMachInst> {
+        size_t operator()(const X86ISA::ExtMachInst &emi) const {
+            return (((uint64_t)emi.legacy << 56) |
+                    ((uint64_t)emi.rex  << 48) |
+                    ((uint64_t)emi.modRM << 40) |
+                    ((uint64_t)emi.sib << 32) |
+                    ((uint64_t)emi.opcode.num << 24) |
+                    ((uint64_t)emi.opcode.prefixA << 16) |
+                    ((uint64_t)emi.opcode.prefixB << 8) |
+                    ((uint64_t)emi.opcode.op)) ^
+                    emi.immediate ^ emi.displacement ^
+                    emi.mode ^
+                    emi.opSize ^ emi.addrSize ^
+                    emi.stackSize ^ emi.dispSize;
+        };
+    };
+}
+
 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
 // and UNSERIALIZE_SCALAR.
 template <>

src/arch/x86/utility.hh

@@ -50,26 +50,6 @@
 
 class ThreadContext;
 
-namespace __hash_namespace {
-    template<>
-    struct hash<X86ISA::ExtMachInst> {
-        size_t operator()(const X86ISA::ExtMachInst &emi) const {
-            return (((uint64_t)emi.legacy << 56) |
-                    ((uint64_t)emi.rex  << 48) |
-                    ((uint64_t)emi.modRM << 40) |
-                    ((uint64_t)emi.sib << 32) |
-                    ((uint64_t)emi.opcode.num << 24) |
-                    ((uint64_t)emi.opcode.prefixA << 16) |
-                    ((uint64_t)emi.opcode.prefixB << 8) |
-                    ((uint64_t)emi.opcode.op)) ^
-                    emi.immediate ^ emi.displacement ^
-                    emi.mode ^
-                    emi.opSize ^ emi.addrSize ^
-                    emi.stackSize ^ emi.dispSize;
-        };
-    };
-}
-
 namespace X86ISA
 {
     uint64_t getArgument(ThreadContext *tc, int number, bool fp);

src/cpu/exetrace.cc

@@ -34,6 +34,7 @@
 #include <iomanip>
 
 #include "arch/isa_traits.hh"
+#include "arch/utility.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"

src/cpu/exetrace.hh

@@ -35,12 +35,12 @@
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "params/ExeTracer.hh"
 #include "sim/insttracer.hh"
 
 class ThreadContext;
 
-
 namespace Trace {
 
 class ExeTracerRecord : public InstRecord

src/cpu/simple_thread.cc

@@ -34,6 +34,7 @@
 #include <string>
 
 #include "arch/isa_traits.hh"
+#include "arch/utility.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"

src/cpu/static_inst.hh

@@ -35,9 +35,8 @@
 #include <string>
 
 #include "arch/isa_traits.hh"
-#include "arch/utility.hh"
+#include "arch/registers.hh"
 #include "config/the_isa.hh"
-#include "base/bitfield.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/refcnt.hh"

src/cpu/thread_context.hh

@@ -31,12 +31,14 @@
 #ifndef __CPU_THREAD_CONTEXT_HH__
 #define __CPU_THREAD_CONTEXT_HH__
 
+#include <string>
+#include <iostream>
+
 #include "arch/registers.hh"
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
-#include "sim/serialize.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
@@ -45,8 +47,8 @@ namespace TheISA
     class TLB;
 }
 class BaseCPU;
+class Checkpoint;
 class EndQuiesceEvent;
-class Event;
 class TranslatingPort;
 class FunctionalPort;
 class VirtualPort;

src/sim/syscall_emul.cc

@@ -36,6 +36,7 @@
 #include <iostream>
 #include <string>
 
+#include "arch/utility.hh"
 #include "sim/syscall_emul.hh"
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"