ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte accesses which could set/clear different numbers of interrupts.
This commit is contained in:
Prakash Ramrakhyani
parent
521d68c82a
commit
9792bbc324
3 changed files with 136 additions and 31 deletions
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@ -51,3 +51,4 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
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Source('realview.cc')
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TraceFlag('AMBA')
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TraceFlag('GIC')
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@ -38,6 +38,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Prakash Ramrakhyani
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*/
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#include "base/trace.hh"
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@ -59,6 +60,8 @@ Gic::Gic(const Params *p)
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cpuEnabled[x] = false;
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cpuPriority[x] = 0;
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cpuBpr[x] = 0;
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// Initialize cpu highest int
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cpuHighestInt[x] = SPURIOUS_INT;
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}
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for (int x = 0; x < 32; x++) {
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@ -146,13 +149,26 @@ Gic::readDistributor(PacketPtr pkt)
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
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Addr int_num;
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int_num = (daddr-ICDIPR_ST) << 2;
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int_num = daddr - ICDIPR_ST;
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assert(int_num < 1020);
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pkt->set<uint32_t>(intPriority[int_num] |
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intPriority[int_num+1] << 8 |
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intPriority[int_num+2] << 16 |
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intPriority[int_num+3] << 24) ;
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DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",int_num);
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switch(pkt->getSize()){
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case 1:
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pkt->set<uint8_t>(intPriority[int_num]);
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break;
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case 2:
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pkt->set<uint16_t>(intPriority[int_num] |
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intPriority[int_num+1] << 8);
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break;
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case 4:
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pkt->set<uint32_t>(intPriority[int_num] |
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intPriority[int_num+1] << 8 |
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intPriority[int_num+2] << 16 |
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intPriority[int_num+3] << 24);
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break;
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default:
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panic("Invalid access size while reading, priority registers in Gic: %d", pkt->getSize());
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}
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goto done;
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}
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@ -223,18 +239,23 @@ Gic::readCpu(PacketPtr pkt)
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break;
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case ICCIAR:
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DPRINTF(Interrupt, "CPU reading IAR = %d\n", cpuHighestInt[0]);
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pkt->set<uint32_t>(cpuHighestInt[0]);
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activeInt[intNumToWord(cpuHighestInt[0])] |=
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1 << intNumToBit(cpuHighestInt[0]);
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pendingInt[intNumToWord(cpuHighestInt[0])] &=
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~(1 << intNumToBit(cpuHighestInt[0]));
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cpuHighestInt[0] = SPURIOUS_INT;
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updateIntState(-1);
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platform->intrctrl->clear(0, ArmISA::INT_IRQ, 0);
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if(enabled && cpuEnabled[0]){
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pkt->set<uint32_t>(cpuHighestInt[0]);
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activeInt[intNumToWord(cpuHighestInt[0])] |=
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1 << intNumToBit(cpuHighestInt[0]);
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updateRunPri();
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pendingInt[intNumToWord(cpuHighestInt[0])] &=
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~(1 << intNumToBit(cpuHighestInt[0]));
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cpuHighestInt[0] = SPURIOUS_INT;
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updateIntState(-1);
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platform->intrctrl->clear(0, ArmISA::INT_IRQ, 0);
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} else {
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pkt->set<uint32_t>(SPURIOUS_INT);
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}
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break;
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case ICCRPR:
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pkt->set<uint32_t>(0);
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panic("Need to implement RPR");
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pkt->set<uint32_t>(iccrpr[0]);
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break;
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case ICCHPIR:
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pkt->set<uint32_t>(0);
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@ -255,8 +276,8 @@ Gic::writeDistributor(PacketPtr pkt)
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Addr daddr = pkt->getAddr() - distAddr;
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pkt->allocate();
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DPRINTF(Interrupt, "gic distributor write register %#x val: %#x\n",
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daddr, pkt->get<uint32_t>());
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DPRINTF(Interrupt, "gic distributor write register %#x size %#x\n",
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daddr, pkt->getSize());
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if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
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assert((daddr-ICDISER_ST) >> 2 < 32);
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@ -285,14 +306,32 @@ Gic::writeDistributor(PacketPtr pkt)
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}
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
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Addr int_num = (daddr-ICDIPR_ST) << 2;
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Addr int_num = daddr - ICDIPR_ST;
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assert(int_num < 1020);
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uint32_t tmp = pkt->get<uint32_t>();
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intPriority[int_num] = tmp & 0xff;
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intPriority[int_num+1] = (tmp >> 8) & 0xff;
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intPriority[int_num+2] = (tmp >> 16) & 0xff;
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intPriority[int_num+3] = (tmp >> 24) & 0xff;
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updateIntState((daddr-ICDIPR_ST)>>2);
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uint32_t tmp;
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switch(pkt->getSize()){
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case 1:
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tmp = pkt->get<uint8_t>();
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intPriority[int_num] = tmp & 0xff;
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break;
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case 2:
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tmp = pkt->get<uint16_t>();
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intPriority[int_num] = tmp & 0xff;
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intPriority[int_num + 1] = (tmp >> 8) & 0xff;
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break;
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case 4:
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tmp = pkt->get<uint32_t>();
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intPriority[int_num] = tmp & 0xff;
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intPriority[int_num + 1] = (tmp >> 8) & 0xff;
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intPriority[int_num + 2] = (tmp >> 16) & 0xff;
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intPriority[int_num + 3] = (tmp >> 24) & 0xff;
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break;
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default:
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panic("Invalid access size while writing to, priority registers in Gic: %d", pkt->getSize());
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}
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updateIntState(-1);
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updateRunPri();
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goto done;
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}
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@ -321,6 +360,7 @@ Gic::writeDistributor(PacketPtr pkt)
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switch(daddr) {
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case ICDDCR:
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enabled = pkt->get<uint32_t>();
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DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
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break;
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case ICDSGIR:
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softInt(pkt->get<uint32_t>());
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@ -363,6 +403,7 @@ Gic::writeCpu(PacketPtr pkt)
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if (!(activeInt[intNumToWord(tmp)] & (1 << intNumToBit(tmp))))
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panic("Done handling interrupt that isn't active?\n");
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activeInt[intNumToWord(tmp)] &= ~(1 << intNumToBit(tmp));
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updateRunPri();
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DPRINTF(Interrupt, "CPU done handling interrupt IAR = %d\n", tmp);
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break;
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default:
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@ -383,10 +424,11 @@ void
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Gic::updateIntState(int hint)
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{
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/*@todo use hint to do less work. */
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int highest_int = -1;
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uint8_t highest_pri = 0xff;
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int highest_int = SPURIOUS_INT;
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// Priorities below that set in ICCPMR can be ignored
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uint8_t highest_pri = cpuPriority[0];
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for (int x = 0; x < itLinesLog2; x++) {
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for (int x = 0; x < (itLines/32) ; x++) {
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if (intEnabled[x] & pendingInt[x]) {
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for (int y = 0; y < 32; y++) {
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if (bits(intEnabled[x], y) & bits(pendingInt[x], y))
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@ -398,7 +440,7 @@ Gic::updateIntState(int hint)
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}
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}
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if (highest_int == -1)
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if (highest_int == SPURIOUS_INT)
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return;
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cpuHighestInt[0] = highest_int;
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@ -406,7 +448,7 @@ Gic::updateIntState(int hint)
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/* @todo make this work for more than one cpu, need to handle 1:N, N:N
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* models */
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if (cpuEnabled[0] && highest_pri < cpuPriority[0]) {
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if (enabled && cpuEnabled[0] && (highest_pri < cpuPriority[0])) {
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/* @todo delay interrupt by some time to deal with calculation delay */
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/* @todo only interrupt if we've haven't already interrupted for this
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* int !!!!!!!!!! */
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@ -415,7 +457,17 @@ Gic::updateIntState(int hint)
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}
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}
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void
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Gic::updateRunPri()
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{
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uint8_t maxPriority = 0xff;
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for (int i = 0 ; i < itLines ; i++){
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if ( activeInt[intNumToWord(i)] & (1 << intNumToBit(i))){
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if (intPriority[i] < maxPriority) maxPriority = intPriority[i];
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}
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}
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iccrpr[0] = maxPriority;
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}
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void
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Gic::sendInt(uint32_t num)
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{
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@ -457,3 +509,40 @@ GicParams::create()
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{
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return new Gic(this);
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}
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/* Functions for debugging and testing */
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void
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Gic::driveSPI(unsigned int spiVect)
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{
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DPRINTF(GIC, "Received SPI Vector:%x Enable: %d\n", spiVect, irqEnable);
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if( irqEnable && enabled ){
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pendingInt[1] |= spiVect;
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updateIntState(-1);
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}
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}
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void
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Gic::driveIrqEn( bool state)
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{
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irqEnable = state;
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}
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void
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Gic::driveLegIRQ(bool state)
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{
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if (irqEnable && !(!enabled && cpuEnabled[0])){
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if(state){
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DPRINTF(GIC, "Driving Legacy Irq\n");
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platform->intrctrl->post(0, ArmISA::INT_IRQ, 0);
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}
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else platform->intrctrl->clear(0, ArmISA::INT_IRQ, 0);
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}
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}
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void
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Gic::driveLegFIQ(bool state)
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{
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if (state)
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platform->intrctrl->post(0, ArmISA::INT_FIQ, 0);
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else platform->intrctrl->clear(0, ArmISA::INT_FIQ, 0);
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}
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@ -138,6 +138,9 @@ class Gic : public PioDevice
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t activeInt[32];
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/** read only running priroity register, 1 per cpu*/
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uint32_t iccrpr[8];
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/** an 8 bit priority (lower is higher priority) for each
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* of the 1020 possible supported interrupts.
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*/
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@ -164,6 +167,9 @@ class Gic : public PioDevice
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/** highest interrupt that is interrupting CPU */
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uint32_t cpuHighestInt[8];
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/** IRQ Enable Used for debug */
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bool irqEnable;
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/** software generated interrupt
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* @param data data to decode that indicates which cpus to interrupt
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*/
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@ -174,6 +180,10 @@ class Gic : public PioDevice
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*/
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void updateIntState(int hint);
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/** Update the register that records priority of the highest priority
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* active interrupt*/
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void updateRunPri();
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int intNumToWord(int num) const { return num >> 5; }
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int intNumToBit(int num) const { return num % 32; }
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@ -232,6 +242,11 @@ class Gic : public PioDevice
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* @param number number of interrupt to send */
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void clearInt(uint32_t number);
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/* Various functions fer testing and debugging */
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void driveSPI(uint32_t spi);
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void driveLegIRQ(bool state);
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void driveLegFIQ(bool state);
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void driveIrqEn(bool state);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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