Commit graph

9153 commits

Author SHA1 Message Date
Anthony Gutierrez
0b3897fc90 O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
2012-08-15 10:38:08 -04:00
Anthony Gutierrez
5a648f2074 configs: add option for repeatedly switching back-and-forth between cpu types.
This patch adds a --repeat-switch option that will enable repeat core
switching at a user defined period (set with --switch-freq option).
currently, a switch can only occur between like CPU types. inorder CPU
switching is not supported.

*note*
this patch simply allows a config that will perform repeat switching, it
does not fix drain/switchout functionality. if you run with repeat switching
you will hit assertion failures and/or your workload with hang or die.
2012-08-15 10:38:07 -04:00
Ali Saidi
73e9e923d0 stats: Update stats for syscall emulation Linux kernel changes. 2012-08-15 10:38:05 -04:00
Ali Saidi
dd1b346584 sysemul: bump all linux versions of for syscal emulation to 3.0.
New tool chains seem to be looking for kernel versions newer than what
this this was previously set to. Also take this opportunity to change
the hostname we report in uname to sim.gem5.org.
2012-08-15 10:38:04 -04:00
Jason Power
11411cc9c7 Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.
2012-08-10 13:50:42 -05:00
Nilay Vaish
706e84f2b8 System: set kernel to null, if unspecified. 2012-08-08 13:40:32 -05:00
Marc Orr
7cef6b9bef syscall emulation: Enabled getrlimit and getrusage for x86.
Added/moved rlimit constants to base linux header file.

This patch is a revised version of Vince Weaver's earlier patch.
2012-08-06 19:52:56 -07:00
Steve Reinhardt
f4b424cd53 SETranslatingPortProxy: fix bug in tryReadString()
Off-by-one loop termination meant that we were stuffing
the terminating '\0' into the std::string value, which
makes for difficult-to-debug string comparison failures.
2012-08-06 16:57:11 -07:00
Steve Reinhardt
73ef8bd168 process: add progName() virtual function
This replaces a (potentially uninitialized) string
field with a virtual function so that we can have
a safe interface without requiring changes to the
eio code.
2012-08-06 16:55:34 -07:00
Steve Reinhardt
e232152db6 syscall_emul: clean up open() code a bit. 2012-08-06 16:55:28 -07:00
Steve Reinhardt
b647b48bf4 str: add an overloaded startswith() utility method
for various string types and use it in a few places.
2012-08-06 16:52:49 -07:00
Marc Orr
d55115936e syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations,
since some use the generic Linux definitions only, and others
use definitions inherited from earlier Unix flavors on those
architectures.

Also update x86 function pointers so ioctl is no longer
unimplemented on that platform.

This patch is a revised version of Vince Weaver's earlier patch.
2012-08-06 16:52:40 -07:00
Nilay Vaish
62425b7a07 Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.
2012-08-06 18:14:32 -05:00
Nilay Vaish
d81a51a4c8 Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.
2012-08-06 18:14:31 -05:00
Jason Power
6721b3e325 Ruby NetDest: add assert for bad element in netdest 2012-08-01 17:07:34 -05:00
Ali Saidi
6a70ef30a3 stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update 2012-07-30 12:11:25 -04:00
Ali Saidi
19cc023cf5 stats: fix some miss-committed changes from the icache change 2012-07-28 13:48:04 -04:00
Nathanael Premillieu
fe2faa1975 util: Fix issues with style checker. 2012-07-27 16:08:05 -04:00
Ali Saidi
b1a58933e0 stats: update stats for icache change not allowing dirty data 2012-07-27 16:08:05 -04:00
Anthony Gutierrez
630068be6f dma: remove unused variable
this patch removes the actionInProgress field from the DmaPort class.
this variable is only defined and initiated in the ctor. it is never used.
2012-07-27 16:08:05 -04:00
Anthony Gutierrez
8133f2460f checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading the
cpu id register failed because the ids did not match, and hence, the result
of the instruction did not match. this patch ensures that the ids match so
this instruction does not fail. this problem only seemed to manifest itself
when multiple cores were in the system, either multi-core, or extra switched-
out cores present in the system.
2012-07-27 16:08:04 -04:00
Anthony Gutierrez
7bf14aedbf cache: don't allow dirty data in the i-cache
removes the optimization that forwards an exclusive copy to a requester on a
read, only for the i-cache. this optimization isn't necessary because we
typically won't be writing to the i-cache.
2012-07-27 16:08:04 -04:00
Anthony Gutierrez
2eb6b403c9 ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ - b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
2012-07-27 16:08:04 -04:00
Andreas Hansson
ae6ab7c03c Config: Use clock option in se/fs script and pass to switch_cpus
This patch changes the se and fs script to use the clock option and
not simply set the CPUs clock to 2 GHz. It also makes a minor change
to the assignment of the switch_cpus clock to allow different clocks.
2012-07-23 09:32:22 -04:00
Andreas Hansson
66f5124e2b Bridge: Use EventWrapper instead of Event subclass for sendEvent
This class simply cleans up the code by making use of the EventWrapper
convenience class to schedule the sendEvent in the bridge ports.
2012-07-23 09:32:19 -04:00
Steve Reinhardt
42596d27e9 test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs
were clobbered.
2012-07-23 00:39:12 -04:00
Steve Reinhardt
882a4b65bd test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
2012-07-23 00:33:05 -04:00
Nilay Vaish
2590a7dd0a Regression: Update stats due to changes to x86 cpuid instruction 2012-07-22 20:31:24 -05:00
Nilay Vaish
11a551ae3a X86 CPUID: Return false if unknown processor family 2012-07-22 20:31:23 -05:00
Andreas Hansson
5e7f174b74 Regression: Fix topologies path in failing pc-simple-timing-ruby
This patch updates the path to the Ruby topologies and thus fixes a
failing regression.
2012-07-21 17:24:01 -04:00
Steve Reinhardt
392ba0131f Added tag stable_2012_06_28 for changeset f75ee4849c40 2012-07-19 16:53:02 -07:00
Steve Reinhardt
c7775731a9 Added tag stable_2012_02_02 for changeset 549b72de8f72 2012-07-19 16:51:01 -07:00
Andreas Hansson
f00cba34eb Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
2012-07-12 12:56:13 -04:00
Andreas Hansson
55bfe13705 scons: Add LIBRARY_PATH from the user environment to Scons
This patch adds the LIBRARY_PATH from the users OS environment to
Scons build environment. This path is used when linking to search for
libraries, and this patch enables tcmalloc to be used during the build
even if it is not placed in the default search paths.
2012-07-12 12:56:11 -04:00
Nilay Vaish
019ced8d85 Regression: update ruby.stats file 2012-07-12 08:39:20 -05:00
Nilay Vaish
b913af440b Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.
2012-07-12 08:39:19 -05:00
Nilay Vaish
ce4e9a9a50 Ruby: remove some unused stuff from SLICC files 2012-07-12 08:39:18 -05:00
Brad Beckmann
8c18f6da9e x86: added page size in bytes tlb entry function 2012-07-11 12:21:04 -07:00
Brad Beckmann
5931087dcd ruby: improved DRAM reset comment 2012-07-11 09:44:34 -07:00
Brad Beckmann
b00fe08cc9 regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
Marc Orr
387f843d51 syscall emulation: Add the futex system call. 2012-07-10 22:51:54 -07:00
Brad Beckmann
52540b1b78 x86: logSize and lruSeq are now optional ckpt params 2012-07-10 22:51:54 -07:00
Steve Reinhardt
2e47aaabc0 Add hook to call map() on Process from python.
This enables configuration scripts to set up mappings
from process virtual addresses to specific physical
addresses in SE mode.  This feature is needed to
support modeling of user-accessible memories or
devices in SE mode, avoiding the complexities of FS
mode and the need to write a device driver.
2012-07-10 22:51:54 -07:00
Brad Beckmann
645fa9c262 # User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed fatal print statement
2012-07-10 22:51:54 -07:00
Brad Beckmann
6f9bd33b73 ruby: remove the cpu assumptions for the random tester 2012-07-10 22:51:54 -07:00
Brad Beckmann
a22918dd41 # User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed msgptr print call
2012-07-10 22:51:54 -07:00
Brad Beckmann
884cd6f752 imported patch jason/slicc-external-structure-fix 2012-07-10 22:51:54 -07:00
Brad Beckmann
86d6b788f6 ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays.  The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute.  This is similar to how TBE entries and slots
in output ports are modeled.
2012-07-10 22:51:54 -07:00
Joel Hestness
467093ebf2 ruby: tag and data cache access support
Updates to Ruby to support statistics counting of cache accesses.  This feature
serves multiple purposes beyond simple stats collection.  It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.
2012-07-10 22:51:54 -07:00
Nuwan Jayasena
c10f348120 ruby: adds reset function to Ruby memory controllers 2012-07-10 22:51:54 -07:00