Ruby: remove some unused stuff from SLICC files

This commit is contained in:
Nilay Vaish 2012-07-12 08:39:18 -05:00
parent 8c18f6da9e
commit ce4e9a9a50
10 changed files with 5 additions and 133 deletions

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@ -28,7 +28,7 @@
*/
// Hack, no node object since base class has them
NodeID id, no_chip_object="yes", no_vector="yes", abstract_chip_ptr="true";
NodeID version, no_chip_object="yes", no_vector="yes", abstract_chip_ptr="true";
MachineID machineID, no_chip_object="yes", no_vector="yes", abstract_chip_ptr="true";
NodeID id;
NodeID version;
MachineID machineID;

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@ -1,6 +1,6 @@
/*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -307,55 +307,6 @@ enumeration(MaskPredictorTraining, "MaskPredictorTraining_Undefined", desc="..."
Both, desc="Both";
}
// Network Topologies
enumeration(TopologyType, desc="...") {
CROSSBAR, desc="One node per chip, single switch crossbar";
HIERARCHICAL_SWITCH, desc="One node per chip, totally ordered hierarchical tree switched network";
TORUS_2D, desc="One node per chip, 2D torus";
PT_TO_PT, desc="One node per chip, Point to Point Network";
FILE_SPECIFIED, desc="described by the file NETWORK_FILE";
}
// DNUCA AllocationStrategy
enumeration(AllocationStrategy, desc="...") {
InMiddle, desc="";
InInvCorners, desc="";
InSharedSides, desc="";
StaticDist, desc="";
RandomBank, desc="";
FrequencyBank, desc="";
FrequencyBlock, desc="";
LRUBlock, desc="";
}
// DNUCA SearchMechanism
enumeration(SearchMechanism, desc="...") {
Perfect, desc="";
PartialTag, desc="";
BloomFilter, desc="";
Random, desc="";
None, desc="";
}
// DNUCA link type
enumeration(LinkType, desc="...") {
RC_1500UM, desc="";
RC_2500UM, desc="";
TL_9000UM, desc="";
TL_11000UM, desc="";
TL_13000UM, desc="";
NO_ENERGY, desc="";
NULL, desc="";
}
// transient request type
enumeration(TransientRequestType, desc="...", default="TransientRequestType_Undefined") {
Undefined, desc="";
OffChip, desc="";
OnChip, desc="";
LocalTransient, desc="";
}
// Request Status
enumeration(RequestStatus, desc="...", default="RequestStatus_NULL") {
Ready, desc="The sequencer is ready and the request does not alias";

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@ -61,7 +61,4 @@ structure(MemoryMsg, desc="...", interface="Message") {
PrefetchBit Prefetch, desc="Is this a prefetch request";
bool ReadX, desc="Exclusive";
int Acks, desc="How many acks to expect";
}

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@ -29,16 +29,9 @@
// Profiler function
void profileStore(NodeID node, bool needCLB);
void profileCacheCLBsize(int size, int numStaleI);
void profileMemoryCLBsize(int size, int numStaleI);
// used by 2level exclusive cache protocols
void profile_miss(RubyRequest msg);
// used by non-fast path protocols
void profile_L1Cache_miss(RubyRequest msg, NodeID l1cacheID);
// used by CMP protocols
void profile_request(std::string L1CacheStateStr, std::string L2CacheStateStr,
std::string directoryStateStr, std::string requestTypeStr);
@ -55,10 +48,3 @@ void profile_average_latency_estimate(int latency);
// profile the total message delay of a message across a virtual network
void profileMsgDelay(int virtualNetwork, int delayCycles);
// used by transactional-memory protocols
void profile_transaction(int numStores);
void profile_trans_wb();
void profileOverflow(Address addr, MachineID mach);

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@ -36,22 +36,13 @@ Time get_time();
Time zero_time();
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Address addr);
bool multicast_retry();
int numberOfNodes();
int numberOfL1CachePerChip();
int getAddThenMod(int addend1, int addend2, int modulus);
int time_to_int(Time time);
Time getTimeModInt(Time time, int modulus);
Time getTimePlusInt(Time addend1, int addend2);
Time getTimeMinusTime(Time t1, Time t2);
Time getPreviousDelayedCycles(Time t1, Time t2);
void procProfileCoherenceRequest(NodeID node, bool needCLB);
void dirProfileCoherenceRequest(NodeID node, bool needCLB);
bool isPerfectProtocol();
bool L1trainsPrefetcher();
int max_tokens();
bool distributedPersistentEnabled();
Address setOffset(Address addr, int offset);
Address makeLineAddress(Address addr);
int addressOffset(Address addr);

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@ -30,7 +30,6 @@
#include "debug/RubyNetwork.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/network/BasicRouter.hh"

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@ -31,7 +31,6 @@
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/BasicLink.hh"

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@ -38,8 +38,6 @@
#include "mem/ruby/common/Address.hh"
#include "mem/packet.hh"
typedef void* RubyPortHandle;
class RubyRequest : public Message
{
public:

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@ -51,7 +51,6 @@ void profile_request(const std::string& L1CacheStateStr,
const std::string& directoryStateStr,
const std::string& requestTypeStr);
void profile_miss(const RubyRequest& msg, NodeID id);
void profile_L1Cache_miss(const RubyRequest& msg, NodeID id);
void profile_token_retry(const Address& addr, AccessType type, int count);
void profile_filter_action(int action);
void profile_persistent_prediction(const Address& addr, AccessType type);

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@ -35,37 +35,17 @@
#include <cassert>
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/system/System.hh"
class Set;
class NetDest;
inline int
random(int n)
{
return random() % n;
}
inline bool
multicast_retry()
{
if (RubySystem::getRandomization()) {
return (random() & 0x1);
} else {
return true;
}
}
inline Time
get_time()
{
@ -92,24 +72,6 @@ IDToInt(NodeID id)
return nodenum;
}
inline int
addressToInt(Address addr)
{
return (int)addr.getLineAddress();
}
inline bool
long_enough_ago(Time event)
{
return ((get_time() - event) > 200);
}
inline int
getAddThenMod(int addend1, int addend2, int modulus)
{
return (addend1 + addend2) % modulus;
}
inline Time
getTimeModInt(Time time, int modulus)
{
@ -129,16 +91,6 @@ getTimeMinusTime(Time t1, Time t2)
return t1 - t2;
}
inline Time
getPreviousDelayedCycles(Time t1, Time t2)
{
if (RubySystem::getRandomization()) { // when randomizing delayed
return 0;
} else {
return getTimeMinusTime(t1, t2);
}
}
// Return type for time_to_int is "Time" and not "int" so we get a
// 64-bit integer
inline Time