Commit graph

10531 commits

Author SHA1 Message Date
Nilay Vaish
02b4605da0 stats: changes to x86 o3 fs and sparc fs regression tests. 2014-11-11 14:17:10 -06:00
Marc Orr
bf80734b2c x86 isa: This patch attempts an implementation at mwait.
Mwait works as follows:
1. A cpu monitors an address of interest (monitor instruction)
2. A cpu calls mwait - this loads the cache line into that cpu's cache.
3. The cpu goes to sleep.
4. When another processor requests write permission for the line, it is
   evicted from the sleeping cpu's cache. This eviction is forwarded to the
   sleeping cpu, which then wakes up.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06 05:42:22 -06:00
Marc Orr
3947f88d0f tests: A test program for the new mwait implementation.
This is a simple test program for the new mwait implemenation. It is uses
m5threads to create to threads of execution in syscall emulation mode that
interact using the mwait instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06 05:42:21 -06:00
Andrew Lukefahr
bd32d55a2c cpu: Minor Draining Bug
Fixes a bug where Minor drains in the midst of committing a
conditional store.

While committing a conditional store, lastCommitWasEndOfMacroop is true
(from the previous instruction) as we still haven't finished the conditional
store. If a drain occurs before the cache response, Minor would check just
lastCommitWasEndOfMacroop, which was true, and set drainState=DrainHaltFetch,
which increases the streamSeqNum.  This caused the conditional store to be
squashed when the memory responded and it completed.  However, to the memory
the store succeeded, while to the instruction sequence it never occurred.

In the case of an LLSC, the instruction sequence will replay the squashed
STREX, which will fail as the cache is no longer in LLSC.  Then the
instruction sequence will loop back to a LDREX, which receives the updated
(incorrect) value.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06 05:42:21 -06:00
Nilay Vaish
a75e27b4a6 stats: updates due to changes to ruby 2014-11-06 05:42:21 -06:00
Nilay Vaish
0811f21f67 ruby: provide a backing store
Ruby's functional accesses are not guaranteed to succeed as of now.  While
this is not a problem for the protocols that are currently in the mainline
repo, it seems that coherence protocols for gpus rely on a backing store to
supply the correct data.  The aim of this patch is to make this backing store
configurable i.e. it comes into play only when a particular option:
--access-backing-store is invoked.

The backing store has been there since M5 and GEMS were integrated.  The only
difference is that earlier the system used to maintain the backing store and
ruby's copy was write-only.  Sometime last year, we moved to data being
supplied supplied by ruby in SE mode simulations.  And now we have patches on
the reviewboard, which remove ruby's copy of memory altogether and rely
completely on the system's memory to supply data.  This patch adds back a
SimpleMemory member to RubySystem.  This member is used only if the option:
access-backing-store is set to true.  By default, the memory would not be
accessed.
2014-11-06 05:42:21 -06:00
Nilay Vaish
3022d463fb ruby: interface with classic memory controller
This patch is the final in the series.  The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system.  This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs.  Classic's memory controller is more up to date and
supports multiple different types of DRAM.  This also brings classic and
ruby ever more close.  The patch also changes ruby's memory controller to
expose the same interface.
2014-11-06 05:42:21 -06:00
Nilay Vaish
68ddfab8a4 ruby: remove the function functionalReadBuffers()
This function was added when I had incorrectly arrived at the conclusion
that such a function can improve the chances of a functional read succeeding.
As was later realized, this is not possible in the current setup.  While the
code using this function was dropped long back, this function was not.  Hence
the patch.
2014-11-06 05:42:20 -06:00
Nilay Vaish
d25b722e4a ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry structure
of each protocol in gem5's mainline.  Firstly, this is required for moving
towards common set of memory controllers for classic and ruby memory systems.
Secondly, the data block was being misused in several places.  It was being
used for having free access to the physical memory instead of calling on the
memory controller.

From now on, the directory controller will not have a direct visibility into
the physical memory.  The Memory Vector object now resides in the
Memory Controller class.  This also means that some significant changes are
being made to the functional accesses in ruby.
2014-11-06 05:42:20 -06:00
Nilay Vaish
0baaed60ab ruby: slicc: allow adding a bool to an int, like C++. 2014-11-06 05:42:20 -06:00
Nilay Vaish
85c29973a3 ruby: remove sparse memory.
In my opinion, it creates needless complications in rest of the code.
Also, this structure hinders the move towards common set of code for
physical memory controllers.
2014-11-06 05:42:20 -06:00
Nilay Vaish
95a0b18431 ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies.  With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations.  This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out.  All the memory accesses now source and sink values
to the memory maintained by ruby.
2014-11-06 05:41:44 -06:00
Nilay Vaish
8ccfd9defa ruby: dma sequencer: remove RubyPort as parent class
As of now DMASequencer inherits from the RubyPort class.  But the code in
RubyPort class is heavily tailored for the CPU Sequencer.  There are parts of
the code that are not required at all for the DMA sequencer.  Moreover, the
next patch uses the dma sequencer for carrying out memory accesses for all the
io devices.  Hence, it is better to have a leaner dma sequencer.
2014-11-06 00:55:09 -06:00
Ali Saidi
ae82551496 tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
2014-11-03 10:14:42 -06:00
Ali Saidi
2c2c3a4ce9 arm, tests: Forgot the system.terminal files for the new regressions. 2014-10-30 00:04:12 -05:00
Ali Saidi
29cd50e14e arm, tests: Add 64-bit ARM regression tests 2014-10-29 23:50:15 -05:00
Ali Saidi
7a0bf814b6 automated merge 2014-10-29 23:22:26 -05:00
Ali Saidi
93c0307d41 tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-29 23:18:29 -05:00
Ali Saidi
f2db2a96d1 arm, tests: Update config files to more recent kernels and create 64-bit regressions.
This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
2014-10-29 23:18:27 -05:00
Mitch Hayenga
5bfa521c46 cpu: Add writeback modeling for drain functionality
It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform a writeback.  This
patch re-adds tracking of in-flight instructions to prevent
falsely signaling a drained event.
2014-10-29 23:18:27 -05:00
Mitch Hayenga
6847bbf7ce cpu: Add drain check functionality to IEW
IEW did not check the instQueue and memDepUnit to ensure
they were drained.  This caused issues when drainSanityCheck()
did check those structures after asserting IEW was drained.
2014-10-29 23:18:26 -05:00
Ali Saidi
b31d9e93e2 arm, mem: Fix drain bug and provide drain prints for more components. 2014-10-29 23:18:26 -05:00
Ali Saidi
baf88e908d arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
2014-10-29 23:18:26 -05:00
Ali Saidi
3a5c975fd7 arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the old scheme
that no-longer works. This change unifies the code so there aren't any differences.
2014-10-29 23:18:26 -05:00
Ali Saidi
9900629f83 arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
2014-10-29 23:18:24 -05:00
Ali Saidi
e3ee27c7b4 cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
2014-10-29 23:18:24 -05:00
Andrew Bardsley
536c72333f cpu: Fix barrier push to store buffer when full bug in Minor
This patch fixes a bug where a completing load or store which is also a
barrier can push a barrier into the store buffer without first checking
that there is a free slot.

The bug was not fatal but would print a warning that the store buffer
was full when inserting.
2014-10-29 23:18:24 -05:00
Curtis Dunham
4024fab7fc mem: don't inhibit WriteInv's or defer snoops on their MSHRs
WriteInvalidate semantics depend on the unconditional writeback
or they won't complete.  Also, there's no point in deferring snoops
on their MSHRs, as they don't get new data at the end of their life
cycle the way other transactions do.

Add comment in the cache about a minor inefficiency re: WriteInvalidate.
2014-10-21 17:04:41 -05:00
Curtis Dunham
46f9f11a55 mem: have WriteInvalidate obsolete MSHRs
Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed.  This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
2014-10-29 23:18:24 -05:00
Steve Reinhardt
6ab4eddb9f syscall_emul: add retry flag to SyscallReturn
This hook allows blocking emulated system calls to indicate
that they would block, but return control to the simulator
so that the simulation does not hang.  The actual retry
functionality requires additional support, to be provided
in a future changeset.
2014-09-02 16:07:50 -05:00
Steve Reinhardt
9ac7f14fc0 syscall_emul: minor style fix to LiveProcess constructor 2014-10-22 15:53:34 -07:00
Steve Reinhardt
df7f0892ed syscall_emul: devirtualize BaseBufferArg methods
Not clear why they were marked virtual to begin with,
but that doesn't appear to be necessary.
2014-10-22 15:53:34 -07:00
Steve Reinhardt
44af2c6a69 syscall_emul: Put BufferArg classes in a separate header.
Move the BufferArg classes that support syscall buffer args
(i.e., pointers into simulated user space) out of syscall_emul.hh
and into a new header syscall_emul_buf.hh so they are accessible
to emulated driver implementations.

Take the opportunity to add some comments as well.
2014-10-22 15:53:34 -07:00
Steve Reinhardt
44ec1d2124 syscall_emul: add EmulatedDriver object
Fake SE-mode device drivers can now be added by
deriving from this abstract object.
2014-10-22 15:53:34 -07:00
Nilay Vaish
6523aad25c sim: revert 6709bbcf564d
The identifier SYS_getdents is not available on Mac OS X.  Therefore, its use
results in compilation failure.  It seems there is no straight forward way to
implement the system call getdents using readdir() or similar C functions.
Hence the commit 6709bbcf564d is being rolled back.
2014-10-22 15:59:57 -05:00
Andreas Hansson
d6f1c6ce89 x86: Fixes to avoid LTO warnings
This patch fixes a few minor issues that caused link-time warnings
when using LTO, mainly for x86. The most important change is how the
syscall array is created. Previously gcc and clang would complain that
the declaration and definition types did not match. The organisation
is now changed to match how it is done for ARM, moving the code that
was previously in syscalls.cc into process.cc, and having a class
variable pointing to the static array.

With these changes, there are no longer any warnings using gcc 4.6.3
with LTO.
2014-10-20 18:03:56 -04:00
Andreas Hansson
6290f98194 misc: Use gmtime for conversion to UTC to avoid getenv/setenv
This patch changes how we turn time into UTC. Previously we
manipulated the TZ environment variable, but this has issues as the
strings that are manipulated could be tainted (see e.g. CERT
ENV34-C). Now we simply rely on the built-in gmtime function and avoid
touching getenv/setenv all together.
2014-10-20 18:03:55 -04:00
Omar Naji
a4a8568bd2 mem: Fix DRAM activationlLimit bug
Ensure that we do the proper event scheduling also when the activation
limit is disabled.
2014-10-20 18:03:55 -04:00
Andreas Hansson
77f8f5d94c base: Fix for stats node on gcc < 4.6.3
This patch adds an explicit function to get the underlying node as gcc
4.6.1 and 4.6.2 have issues otherwise.
2014-10-20 18:03:54 -04:00
Andreas Hansson
b976496a34 ext: Bump DRAMPower to avoid compilation issues
This patch bumps DRAMPower to commit
19433a6897ede4bbb19b06694faa8589b5a6569a which contains a small fix
for clang, and a work-around for LTO with gcc 4.6.
2014-10-20 18:03:53 -04:00
Omar Naji
29dd2887f4 mem: Add DRAM device size and check against config
This patch adds the size of the DRAM device to the DRAM config. It
also compares the actual DRAM size (calculated using information from
the config) to the size defined in the system. If these two values do
not match gem5 will print a warning. In order to do correct DRAM
research the size of the memory defined in the system should match the
size of the DRAM in the config. The timing and current parameters
found in the DRAM configs are defined for a DRAM device with a
specific size and would differ for another device with a different
size.
2014-10-20 18:03:52 -04:00
Nilay Vaish
d2a0f60b69 stats: updates due to previous mmap and exit_group patches. 2014-10-20 16:48:19 -05:00
Nilay Vaish
922a9d8ed2 cpu: o3: corrects base FP and CC register index in removeThread() 2014-10-20 16:47:55 -05:00
Tom Jablin
c6731e331a sim: invalid alignment checks in mmap and mremap
Presently, the alignment checks in the mmap and mremap implementations
in syscall_emul.hh are wrong. The checks are implemented as:

if ((start % TheISA::PageBytes) != 0 ||
        (length % TheISA::PageBytes) != 0) {
    warn("mmap failing: arguments not page-aligned: "
            "start 0x%x length 0x%x",
            start, length);
    return -EINVAL;
}

This checks that both the start and the length arguments of the mmap
syscall are checked for page-alignment. However, the POSIX specification says:

The off argument is constrained to be aligned and sized according to the value
returned by sysconf() when passed _SC_PAGESIZE or _SC_PAGE_SIZE. When MAP_FIXED
is specified, the application shall ensure that the argument addr also meets
these constraints. The implementation performs mapping operations over whole
pages. Thus, while the argument len need not meet a size or alignment
constraint, the implementation shall include, in any mapping operation, any
partial page specified by the range [pa,pa+len).

So the length parameter should not be checked for page-alignment. By contrast,
the current implementation fails to check the offset argument, which must be
page aligned.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:45:25 -05:00
Michael Adler
7254d5742a sim: mmap: correct behavior for fixed address
Change mmap fixed address request to return an error if the mapping is
impossible due to conflict instead of what I believe used to be silent
corruption.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:45:08 -05:00
Michael Adler
a3fe4c0662 sim: implement getdents/getdents64 in user mode
Has been tested only for alpha.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:44:53 -05:00
Severin Wischmann ext:(%2C%20Ioannis%20Ilkos%20%3Cioannis.ilkos09%40imperial.ac.uk%3E)
e72736aaf0 x86: syscall: implementation of exit_group
On exit_group syscall, we used to exit the simulator.  But now we will only
halt the execution of threads that belong to the group.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-20 16:43:48 -05:00
Andreas Hansson
6d4866383f mem: Modernise PhysicalMemory with C++11 features
Bring the PhysicalMemory up-to-date by making use of range-based for
loops and vector intialisation where possible.
2014-10-16 05:50:01 -04:00
Andreas Hansson
edc77fc03c misc: Move AddrRangeList from port.hh to addr_range.hh
The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.
2014-10-16 05:49:59 -04:00
Andreas Sandberg
e6ad39adac ext: Update fputils to rev 6a47fd8358
This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository (github.com/andysan/fputils). Most notably,
this includes changes that export a limited set of 64-bit float
manipulation and avoids a warning about unused 64-bit floats in clang.
2014-10-16 05:49:58 -04:00