stats: Get all stats updated to reflect current behaviour
Line everything up again.
This commit is contained in:
Andreas Hansson
parent
184c6d7ebd
commit
f2e2410a50
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,43 +1,43 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.225207 # Number of seconds simulated
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sim_ticks 225206521000 # Number of ticks simulated
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final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.225185 # Number of seconds simulated
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sim_ticks 225184887000 # Number of ticks simulated
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final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 289736 # Simulator instruction rate (inst/s)
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host_op_rate 347860 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 238979319 # Simulator tick rate (ticks/s)
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host_mem_usage 279872 # Number of bytes of host memory used
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host_seconds 942.37 # Real time elapsed on the host
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host_inst_rate 292846 # Simulator instruction rate (inst/s)
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host_op_rate 351594 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 241521552 # Simulator tick rate (ticks/s)
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host_mem_usage 280036 # Number of bytes of host memory used
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host_seconds 932.36 # Real time elapsed on the host
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sim_insts 273037855 # Number of instructions simulated
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sim_ops 327812212 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
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system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
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system.physmem.bytes_read::total 485568 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
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system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7587 # Number of read requests accepted
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system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7586 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM
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system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side
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system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::11 428 # Pe
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system.physmem.perBankRdBursts::12 553 # Per bank write bursts
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system.physmem.perBankRdBursts::13 705 # Per bank write bursts
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system.physmem.perBankRdBursts::14 639 # Per bank write bursts
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system.physmem.perBankRdBursts::15 543 # Per bank write bursts
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system.physmem.perBankRdBursts::15 542 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 225206267000 # Total gap between requests
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system.physmem.totGap 225184633000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 7587 # Read request sizes (log2)
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system.physmem.readPktSize::6 7586 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
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system.physmem.totQLat 232471000 # Total ticks spent queuing
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system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst
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system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation
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system.physmem.totQLat 232077250 # Total ticks spent queuing
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system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst
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system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
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@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.02 # Da
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 6073 # Number of row buffer hits during reads
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system.physmem.readRowHits 6074 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
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system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 29683177.41 # Average gap between requests
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system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
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system.physmem.avgGap 29684238.47 # Average gap between requests
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system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
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system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ)
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system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ)
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system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
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system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ)
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system.physmem_0.averagePower 244.071435 # Core power per rank (mW)
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system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank
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system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
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system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ)
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system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ)
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system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ)
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system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ)
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system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ)
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system.physmem_0.averagePower 244.071899 # Core power per rank (mW)
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system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank
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system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states
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system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
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system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
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system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states
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system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
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system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ)
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system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
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system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
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system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
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system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
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system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
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system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
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system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ)
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system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ)
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system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ)
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system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ)
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system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ)
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system.physmem_1.averagePower 245.505612 # Core power per rank (mW)
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system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank
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system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states
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system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states
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system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
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system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
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system.cpu.branchPred.lookups 32430299 # Number of BP lookups
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system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
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system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states
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system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
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system.cpu.branchPred.lookups 32421416 # Number of BP lookups
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system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches.
|
||||
system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 450413042 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 450369774 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037855 # Number of instructions committed
|
||||
system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.649636 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.606194 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.649477 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.606253 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
|
||||
|
|
@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 327812212 # Class of committed instruction
|
||||
system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1355 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
|
|
@ -465,23 +465,23 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168625687 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses
|
||||
|
|
@ -492,28 +492,28 @@ system.cpu.dcache.demand_misses::cpu.data 6940 # n
|
|||
system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6945 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
|
||||
|
|
@ -524,14 +524,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -558,16 +558,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509
|
|||
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -578,24 +578,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 38188 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 38251 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
||||
|
|
@ -605,179 +605,179 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 32
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 69819801 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 40126 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 69805458 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 40189 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 38188 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 38188 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.writebacks::writebacks 38251 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 38251 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
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|
||||
system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_accesses::total 44638 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 40126 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 44638 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085381 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085381 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses
|
||||
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|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses
|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses
|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -796,122 +796,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 41
|
|||
system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 4732 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 7587 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 7586 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7587 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 7586 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.132539 # Number of seconds simulated
|
||||
sim_ticks 132538562500 # Number of ticks simulated
|
||||
final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.132570 # Number of seconds simulated
|
||||
sim_ticks 132570000500 # Number of ticks simulated
|
||||
final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 360845 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 380389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 277544932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274852 # Number of bytes of host memory used
|
||||
host_seconds 477.54 # Real time elapsed on the host
|
||||
host_inst_rate 373440 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 393666 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 287300012 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274936 # Number of bytes of host memory used
|
||||
host_seconds 461.43 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 247552 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3868 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 132538461500 # Total gap between requests
|
||||
system.physmem.totGap 132569899500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh
|
|||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 84421250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 82551750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -221,62 +221,62 @@ system.physmem.readRowHits 2935 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 34265372.67 # Average gap between requests
|
||||
system.physmem.avgGap 34273500.39 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 244.088313 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states
|
||||
system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 244.026270 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states
|
||||
system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 243.767063 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 49693791 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits
|
||||
system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 243.774090 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 49693872 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches.
|
||||
system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 265077125 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 265140001 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317810 # Number of instructions committed
|
||||
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.538304 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.650067 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.538669 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.649913 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
||||
|
|
@ -446,18 +446,18 @@ system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 181650743 # Class of committed instruction
|
||||
system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
|
||||
|
|
@ -465,73 +465,73 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 85
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40710583 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40709647 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2406 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2405 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -542,12 +542,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu
|
|||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
|
||||
|
|
@ -558,162 +558,162 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810
|
|||
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 2864 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 2861 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 70941363 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4664 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 70991309 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4661 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 2864 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2864 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.writebacks::writebacks 2861 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2861 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2590 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2502 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2590 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2587 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses
|
||||
|
|
@ -726,58 +726,58 @@ system.cpu.l2cache.demand_misses::total 3885 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4664 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -806,79 +806,79 @@ system.cpu.l2cache.demand_mshr_misses::total 3869
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -888,7 +888,7 @@ system.membus.snoop_filter.hit_multi_requests 0
|
|||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 2777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
|
||||
|
|
@ -909,9 +909,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3868 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu
|
|||
sim_ticks 41083000 # Number of ticks simulated
|
||||
final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 217103 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 217013 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1389706699 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253264 # Number of bytes of host memory used
|
||||
host_inst_rate 202272 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 202193 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1294825774 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252636 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 6413 # Number of instructions simulated
|
||||
sim_ops 6413 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # By
|
|||
system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 6580250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 6584250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -247,9 +247,9 @@ system.physmem_1.preEnergy 208725 # En
|
|||
system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ)
|
||||
|
|
@ -262,19 +262,19 @@ system.physmem_1.memoryStateTime::PRE_PDN 464250 # T
|
|||
system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 2003 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups
|
||||
system.cpu.branchPred.lookups 2002 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 377 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 322 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
|
||||
system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 319 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -292,10 +292,10 @@ system.cpu.dtb.data_hits 2249 # DT
|
|||
system.cpu.dtb.data_misses 14 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2263 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2686 # ITB hits
|
||||
system.cpu.itb.fetch_hits 2685 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2703 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 2702 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -315,7 +315,7 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6413 # Number of instructions committed
|
||||
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 12.812412 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.078049 # IPC: instructions per cycle
|
||||
|
|
@ -358,18 +358,18 @@ system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 6413 # Class of committed instruction
|
||||
system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
|
||||
|
|
@ -395,12 +395,12 @@ system.cpu.dcache.overall_misses::cpu.data 221 #
|
|||
system.cpu.dcache.overall_misses::total 221 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -419,12 +419,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.099955
|
|||
system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -447,12 +447,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 169
|
|||
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -463,65 +463,65 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5736 # Number of data accesses
|
||||
system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5734 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2322 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2321 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -534,33 +534,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364
|
|||
system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy
|
||||
|
|
@ -589,18 +589,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 532 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -625,18 +625,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -655,18 +655,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -679,18 +679,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -755,7 +755,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 532 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000112 # Nu
|
|||
sim_ticks 112490 # Number of ticks simulated
|
||||
final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 109209 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 109187 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1917933 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 416076 # Number of bytes of host memory used
|
||||
host_inst_rate 109524 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 109501 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1923375 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 415960 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -414,13 +414,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.333412
|
|||
system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 1731
|
||||
system.ruby.Directory.incomplete_times_seqr 1730
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997813 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743091 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999387 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999396 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.984319 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.075242 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061480 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999947 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995333 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.986612 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.996053 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092150 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.743802 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.685128
|
||||
system.ruby.network.routers0.msg_count.Control::2 1731
|
||||
|
|
@ -431,6 +453,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 124344
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743268 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995609 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998755 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.685128
|
||||
system.ruby.network.routers1.msg_count.Control::2 1731
|
||||
|
|
@ -441,6 +469,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 124344
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.743695 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.993386 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.998107 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.988888 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.996755 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.743428 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.991146 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997440 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.743571 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.685128
|
||||
system.ruby.network.routers2.msg_count.Control::2 1731
|
||||
|
|
|
|||
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32719500 # Number of ticks simulated
|
||||
final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 32617500 # Number of ticks simulated
|
||||
final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 128948 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 150916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 915725978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269308 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 159604 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 186772 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1129633158 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268376 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 421 # Number of read requests accepted
|
||||
system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 420 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
|
||||
system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
|
|
@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 91 # Pe
|
|||
system.physmem.perBankRdBursts::1 52 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 43 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 22 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 21 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 41 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 36 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 12 # Per bank write bursts
|
||||
|
|
@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 32621500 # Total gap between requests
|
||||
system.physmem.totGap 32519500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 421 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 420 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh
|
|||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 5175000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst
|
||||
system.physmem.totQLat 5148000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 6.43 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 6.44 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 347 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 346 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 77485.75 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 77427.38 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 615.992054 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 616.275926 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states
|
||||
system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 556.500000 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 557.213152 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1968 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 322 # Number of BTB hits
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1965 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 324 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 127 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
|
||||
system.cpu.branchPred.indirectMisses 129 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 65439 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 65235 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4605 # Number of instructions committed
|
||||
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 14.210423 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.070371 # IPC: instructions per cycle
|
||||
system.cpu.cpi 14.166124 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.070591 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
|
||||
|
|
@ -446,25 +446,25 @@ system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 5391 # Class of committed instruction
|
||||
system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
|
||||
|
|
@ -567,59 +567,59 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658
|
|||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4896 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1965 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 322 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4895 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1966 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 321 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -628,49 +628,49 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 4 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
|
||||
|
|
@ -685,66 +685,66 @@ system.cpu.l2cache.overall_hits::cpu.data 22 # n
|
|||
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 428 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -759,120 +759,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 8
|
|||
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter.
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 378 # Transaction distribution
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 377 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 421 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 420 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 421 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 420 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 20302000 # Number of ticks simulated
|
||||
final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 10367 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12141 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45828431 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248616 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
host_inst_rate 93691 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 109699 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 414022055 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265936 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -205,12 +205,12 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By
|
|||
system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 6124000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 6135000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -232,28 +232,28 @@ system.physmem_0.preEnergy 170775 # En
|
|||
system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 656.916882 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states
|
||||
system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ)
|
||||
|
|
@ -267,12 +267,12 @@ system.physmem_1.memoryStateTime::ACT 2792000 # Ti
|
|||
system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 2438 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 449 # Number of BTB hits
|
||||
system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 446 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups.
|
||||
|
|
@ -405,80 +405,80 @@ system.cpu.pwrStateResidencyTicks::ON 20302000 # Cu
|
|||
system.cpu.numCycles 40605 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5174 # Number of cycles decode is running
|
||||
system.cpu.decode.RunCycles 5171 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch
|
||||
system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle
|
||||
system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 4185 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 4182 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -487,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 7222 # Type of FU issued
|
||||
system.cpu.iq.rate 0.177860 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 7227 # Type of FU issued
|
||||
system.cpu.iq.rate 0.177983 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads
|
||||
system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 13 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 2442 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1297 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 2443 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1299 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1024 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.167836 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 6631 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2981 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 5426 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back
|
||||
system.cpu.iew.exec_rate 0.168033 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 6639 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2983 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 5430 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle
|
||||
|
|
@ -635,7 +635,7 @@ system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4592 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 23226 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 16730 # The number of ROB writes
|
||||
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 23224 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 16731 # The number of ROB writes
|
||||
system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4592 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 6765 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 3787 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 6850 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 3795 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.cc_regfile_reads 24202 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 2924 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 2558 # number of misc regfile reads
|
||||
system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 2927 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 2559 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
||||
|
|
@ -720,38 +720,38 @@ system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344
|
|||
system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1906 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1903 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 358 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 361 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -764,26 +764,26 @@ system.cpu.dcache.demand_accesses::cpu.data 2264 #
|
|||
system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -792,16 +792,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
|
||||
|
|
@ -810,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144
|
|||
system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -826,67 +826,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 44 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
|
||||
system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 8095 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 3536 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 3532 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 366 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked
|
||||
|
|
@ -895,36 +895,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 44 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 44 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
|
||||
|
|
@ -934,16 +934,16 @@ system.cpu.l2cache.prefetcher.pfRemovedFull 0 #
|
|||
system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
|
||||
|
|
@ -981,16 +981,16 @@ system.cpu.l2cache.overall_misses::cpu.data 133 #
|
|||
system.cpu.l2cache.overall_misses::total 424 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -1019,16 +1019,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1064,17 +1064,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766
|
|||
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -1094,17 +1094,17 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338
|
|||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -1173,7 +1173,7 @@ system.membus.snoop_fanout::max_value 0 # Re
|
|||
system.membus.snoop_fanout::total 445 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 24405000 # Number of ticks simulated
|
||||
final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 38911 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38904 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189891987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234100 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 119579 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 119550 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 583509526 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251420 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 4999 # Number of instructions simulated
|
||||
sim_ops 4999 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By
|
|||
system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 7577250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 7589250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -228,9 +228,9 @@ system.physmem_0.preEnergy 98670 # En
|
|||
system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ)
|
||||
|
|
@ -247,29 +247,29 @@ system.physmem_1.preEnergy 333960 # En
|
|||
system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 675.693915 # Core power per rank (mW)
|
||||
system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 675.712354 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 2188 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 587 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 2177 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 589 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
|
||||
|
|
@ -299,91 +299,91 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu
|
|||
system.cpu.numCycles 48811 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2768 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch
|
||||
system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2766 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking
|
||||
system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 2740 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 2736 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
|
||||
|
|
@ -423,58 +423,58 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8118 # Type of FU issued
|
||||
system.cpu.iq.rate 0.166315 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 8108 # Type of FU issued
|
||||
system.cpu.iq.rate 0.166110 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
|
||||
|
|
@ -483,45 +483,45 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 1596 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1363 # Number of branches executed
|
||||
system.cpu.iew.exec_nop 1594 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3172 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1361 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1049 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.159595 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7339 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2867 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4274 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit
|
||||
system.cpu.iew.exec_rate 0.159308 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7331 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2863 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4269 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle
|
||||
|
|
@ -531,7 +531,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 5640 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 24800 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22133 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 24772 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22085 # The number of ROB writes
|
||||
system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4999 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10560 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5141 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 10585 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5135 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 161 # number of misc regfile reads
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 91.124976 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2389 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 17.064286 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 91.124976 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022247 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022247 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 5940 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 5940 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2395 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 2389 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses
|
||||
|
|
@ -638,22 +638,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 46928999
|
|||
system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2900 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2900 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083542 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.083542 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.176207 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.176207 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.176207 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.176207 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency
|
||||
|
|
@ -692,14 +692,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499
|
|||
system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.048276 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.048276 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency
|
||||
|
|
@ -710,57 +710,57 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 160.153151 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.846386 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 160.153151 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078200 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078200 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4432 # Number of data accesses
|
||||
system.cpu.icache.tags.tag_accesses 4424 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4424 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1613 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1609 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 437 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35547000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 35547000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 35547000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 35547000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 35547000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 35547000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2046 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2046 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2046 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2046 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.213587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.213587 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.213587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.213587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.213587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81343.249428 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 81343.249428 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 81343.249428 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 81343.249428 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -781,36 +781,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332
|
|||
system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28124000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 28124000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28124000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 28124000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28124000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 28124000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162268 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.162268 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.162268 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84710.843373 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84710.843373 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 253.368786 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.183576 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 91.185210 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004949 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007732 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
|
||||
|
|
@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 #
|
|||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27593000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27593000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27593000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 40389500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27593000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 40389500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83869.300912 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83869.300912 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 86118.336887 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 86118.336887 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140
|
|||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24303000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24303000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24303000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 35699500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24303000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 35699500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu
|
|||
sim_ticks 106125 # Number of ticks simulated
|
||||
final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 110472 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2077956 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 415232 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 95829 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95814 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1802278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414992 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_ops 5641 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.614530
|
|||
system.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 1472
|
||||
system.ruby.Directory.incomplete_times_seqr 1471
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997663 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.765826 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999350 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999359 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.983246 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.072357 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.055406 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999943 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995053 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.985696 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995816 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.083033 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.766579 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 6.925795
|
||||
system.ruby.network.routers0.msg_count.Control::2 1472
|
||||
|
|
@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 105696
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 105984
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.766014 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995307 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998681 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 6.925795
|
||||
system.ruby.network.routers1.msg_count.Control::2 1472
|
||||
|
|
@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 105696
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 105984
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.766466 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.992933 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.997993 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.988127 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.996561 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.766184 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.990540 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997286 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.027703 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.766334 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 6.925795
|
||||
system.ruby.network.routers2.msg_count.Control::2 1472
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
|
|||
sim_ticks 14435000 # Number of ticks simulated
|
||||
final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 13240 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 13237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 119615611 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232036 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 136295 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 136181 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1229999304 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249560 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 1597 # Number of instructions simulated
|
||||
sim_ops 1597 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -261,16 +261,16 @@ system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cu
|
|||
system.cpu.branchPred.lookups 995 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 100 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 11 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 193 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches.
|
||||
system.cpu.branchPred.indirectMisses 191 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu
|
|||
sim_ticks 7939500 # Number of ticks simulated
|
||||
final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22942 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22935 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 114711600 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232976 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 81718 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81674 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 408398393 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251348 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 1587 # Number of instructions simulated
|
||||
sim_ops 1587 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -258,18 +258,18 @@ system.physmem_1.memoryStateTime::PRE_PDN 0 # T
|
|||
system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1252 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 1255 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 300 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 302 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 228 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -296,9 +296,9 @@ system.cpu.numCycles 15880 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
|
|
@ -307,71 +307,71 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 1 #
|
|||
system.cpu.fetch.CacheLines 803 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 756 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking
|
||||
system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 672 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 673 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename
|
||||
system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups
|
||||
system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -417,73 +417,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 2694 # Type of FU issued
|
||||
system.cpu.iq.rate 0.169647 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 2703 # Type of FU issued
|
||||
system.cpu.iq.rate 0.170214 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 70 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -491,41 +491,41 @@ system.cpu.iew.memOrderViolationEvents 1 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 847 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 563 # Number of branches executed
|
||||
system.cpu.iew.exec_refs 846 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 566 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 375 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.154408 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2310 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 793 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1130 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit
|
||||
system.cpu.iew.exec_rate 0.154849 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2318 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 798 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1140 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 1587 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -576,8 +576,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 1587 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 7041 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6340 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 7050 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6361 # The number of ROB writes
|
||||
system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1587 # Number of Instructions Simulated
|
||||
|
|
@ -586,14 +586,14 @@ system.cpu.cpi 10.006301 # CP
|
|||
system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3068 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1663 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 3116 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1668 # number of integer regfile writes
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy
|
||||
|
|
@ -601,17 +601,17 @@ system.cpu.dcache.tags.occ_percent::total 0.005903 # A
|
|||
system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 626 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 625 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
|
||||
|
|
@ -628,22 +628,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7406500
|
|||
system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency
|
||||
|
|
@ -682,14 +682,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500
|
|||
system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 27947 # Number of ticks simulated
|
||||
final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19868 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19863 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 349695 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390760 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 89967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1582597 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409032 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 1587 # Number of instructions simulated
|
||||
sim_ops 1587 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -397,13 +397,35 @@ system.ruby.miss_latency_hist_seqr::stdev 27.345330
|
|||
system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 438
|
||||
system.ruby.Directory.incomplete_times_seqr 437
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.986546 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.686704 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997531 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997567 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.904322 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077501 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999964 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.062402 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999785 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.981215 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.918205 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.984113 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.093316 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.689566 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.800479
|
||||
system.ruby.network.routers0.msg_count.Control::2 438
|
||||
|
|
@ -414,6 +436,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 3504
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 31248
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 31536
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.687419 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.973021 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.994991 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.800479
|
||||
system.ruby.network.routers1.msg_count.Control::2 438
|
||||
|
|
@ -424,6 +452,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 3504
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 31248
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 31536
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.689137 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.959425 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.992379 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.932017 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.986940 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.688064 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.945756 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.989695 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.031201 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.688636 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.800479
|
||||
system.ruby.network.routers2.msg_count.Control::2 438
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu
|
|||
sim_ticks 86746 # Number of ticks simulated
|
||||
final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 115505 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 115448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1879120 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414144 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 122857 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 122829 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1999767 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 415460 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -381,13 +381,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665
|
|||
system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 1289
|
||||
system.ruby.Directory.incomplete_times_seqr 1288
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.418209
|
||||
system.ruby.network.routers0.msg_count.Control::2 1289
|
||||
|
|
@ -398,6 +420,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.418209
|
||||
system.ruby.network.routers1.msg_count.Control::2 1289
|
||||
|
|
@ -408,6 +436,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.418209
|
||||
system.ruby.network.routers2.msg_count.Control::2 1289
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000092 # Nu
|
|||
sim_ticks 91859 # Number of ticks simulated
|
||||
final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 91408 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 165563 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1559913 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 432272 # Number of bytes of host memory used
|
||||
host_inst_rate 94122 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 170479 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1606243 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 432368 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -388,13 +388,35 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423
|
|||
system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 1377
|
||||
system.ruby.Directory.incomplete_times_seqr 1376
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.484297
|
||||
system.ruby.network.routers0.msg_count.Control::2 1377
|
||||
|
|
@ -405,6 +427,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.484297
|
||||
system.ruby.network.routers1.msg_count.Control::2 1377
|
||||
|
|
@ -415,6 +443,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.484297
|
||||
system.ruby.network.routers2.msg_count.Control::2 1377
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000167 # Number of seconds simulated
|
||||
sim_ticks 167328500 # Number of ticks simulated
|
||||
final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 167318000 # Number of ticks simulated
|
||||
final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 54302 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 54316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79708249 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244184 # Number of bytes of host memory used
|
||||
host_seconds 2.10 # Real time elapsed on the host
|
||||
host_inst_rate 259842 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 259907 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 381385356 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261864 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
sim_insts 113991 # Number of instructions simulated
|
||||
sim_ops 114022 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 69760 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 52672 # Nu
|
|||
system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1090 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 166995000 # Total gap between requests
|
||||
system.physmem.totGap 166987000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -201,15 +201,15 @@ system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # By
|
|||
system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 15434500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 15449500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 3.26 # Data bus utilization in percentage
|
||||
|
|
@ -221,59 +221,59 @@ system.physmem.readRowHits 874 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 153206.42 # Average gap between requests
|
||||
system.physmem.avgGap 153199.08 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 555.501490 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 555.517657 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states
|
||||
system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 539.085991 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 539.101715 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 31621 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15507 # Number of BTB hits
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 31578 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15512 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 43 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 334657 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 334636 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 113991 # Number of instructions committed
|
||||
system.cpu.committedOps 114022 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 2.935819 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.340620 # IPC: instructions per cycle
|
||||
system.cpu.cpi 2.935635 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.340642 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction
|
||||
|
|
@ -344,38 +344,38 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 114022 # Class of committed instruction
|
||||
system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44060 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44057 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
|
||||
|
|
@ -384,42 +384,42 @@ system.cpu.dcache.demand_misses::cpu.data 459 # n
|
|||
system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 459 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -442,14 +442,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 268
|
|||
system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -458,68 +458,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 18 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 101823 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49677 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 101789 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49660 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 823 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -534,36 +534,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823
|
|||
system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id
|
||||
|
|
@ -571,7 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
|
||||
|
|
@ -594,16 +594,16 @@ system.cpu.l2cache.overall_misses::cpu.data 267 #
|
|||
system.cpu.l2cache.overall_misses::total 1090 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -632,16 +632,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -662,16 +662,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 267
|
|||
system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -686,23 +686,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution
|
||||
|
|
@ -740,7 +740,7 @@ system.membus.snoop_filter.hit_multi_requests 0
|
|||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 891 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 199 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 199 # Transaction distribution
|
||||
|
|
@ -761,7 +761,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1090 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000796 # Nu
|
|||
sim_ticks 796036 # Number of ticks simulated
|
||||
final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51863 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51862 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 623875 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411084 # Number of bytes of host memory used
|
||||
host_seconds 1.28 # Real time elapsed on the host
|
||||
host_inst_rate 163786 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1970174 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 428500 # Number of bytes of host memory used
|
||||
host_seconds 0.40 # Real time elapsed on the host
|
||||
sim_insts 66173 # Number of instructions simulated
|
||||
sim_ops 66173 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 31.144722
|
|||
system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 14050
|
||||
system.ruby.Directory.incomplete_times_seqr 14049
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999377 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.715164 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999913 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999915 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.995586 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.113609 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.070590 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999992 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999340 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.996224 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999442 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.105874 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.715264 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 8.823722
|
||||
system.ruby.network.routers0.msg_count.Control::2 14050
|
||||
|
|
@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 112400
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 1011312
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.715189 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.998751 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999824 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 8.823722
|
||||
system.ruby.network.routers1.msg_count.Control::2 14050
|
||||
|
|
@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 112400
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 1011312
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.715249 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.998123 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.999732 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.996859 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.999541 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.715212 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.997493 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999638 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.035295 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.715232 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 8.823722
|
||||
system.ruby.network.routers2.msg_count.Control::2 14050
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000339 # Number of seconds simulated
|
||||
sim_ticks 339160000 # Number of ticks simulated
|
||||
final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 339173000 # Number of ticks simulated
|
||||
final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25032 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25032 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28360795 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244952 # Number of bytes of host memory used
|
||||
host_seconds 11.96 # Real time elapsed on the host
|
||||
host_inst_rate 215547 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 215545 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 244214530 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263004 # Number of bytes of host memory used
|
||||
host_seconds 1.39 # Real time elapsed on the host
|
||||
sim_insts 299354 # Number of instructions simulated
|
||||
sim_ops 299354 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 95040 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 74688 # Nu
|
|||
system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1485 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 338943500 # Total gap between requests
|
||||
system.physmem.totGap 338956500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh
|
|||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 19805250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 20061750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 2.19 # Data bus utilization in percentage
|
||||
|
|
@ -221,58 +221,58 @@ system.physmem.readRowHits 1195 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 228244.78 # Average gap between requests
|
||||
system.physmem.avgGap 228253.54 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 553.629673 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states
|
||||
system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 553.841711 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states
|
||||
system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 537.082660 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states
|
||||
system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 536.767851 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 80709 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 38294 # Number of BTB hits
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 80662 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 38260 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 162 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 678320 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 678346 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 299354 # Number of instructions committed
|
||||
system.cpu.committedOps 299354 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 2.265946 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.441317 # IPC: instructions per cycle
|
||||
system.cpu.cpi 2.266033 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.441300 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction
|
||||
|
|
@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 299354 # Class of committed instruction
|
||||
system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 119907 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 119892 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses
|
||||
|
|
@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n
|
|||
system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 511 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses
|
||||
|
|
@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004244
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -432,84 +432,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 320
|
|||
system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 80 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 273696 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 135081 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 273390 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 134928 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1178 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -524,36 +524,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1178
|
|||
system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
||||
|
|
@ -561,7 +561,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits
|
||||
|
|
@ -588,16 +588,16 @@ system.cpu.l2cache.overall_misses::cpu.data 318 #
|
|||
system.cpu.l2cache.overall_misses::total 1485 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -626,16 +626,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -656,16 +656,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 318
|
|||
system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -680,23 +680,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution
|
||||
|
|
@ -734,7 +734,7 @@ system.membus.snoop_filter.hit_multi_requests 0
|
|||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1283 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 202 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 202 # Transaction distribution
|
||||
|
|
@ -755,9 +755,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1485 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.006394 # Nu
|
|||
sim_ticks 6393532 # Number of ticks simulated
|
||||
final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 13428 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 13428 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 286950 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412476 # Number of bytes of host memory used
|
||||
host_seconds 22.28 # Real time elapsed on the host
|
||||
host_inst_rate 80438 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 80438 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1718903 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429644 # Number of bytes of host memory used
|
||||
host_seconds 3.72 # Real time elapsed on the host
|
||||
sim_insts 299191 # Number of instructions simulated
|
||||
sim_ops 299191 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -403,13 +403,35 @@ system.ruby.miss_latency_hist_seqr::stdev 36.989317
|
|||
system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 97760
|
||||
system.ruby.Directory.incomplete_times_seqr 97759
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999944 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.755056 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999599 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.065339 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061161 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999918 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999657 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999931 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091740 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755068 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.645070
|
||||
system.ruby.network.routers0.msg_count.Control::2 97760
|
||||
|
|
@ -420,6 +442,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 782080
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 7038432
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755059 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999887 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999978 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.645070
|
||||
system.ruby.network.routers1.msg_count.Control::2 97760
|
||||
|
|
@ -430,6 +458,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 782080
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 7038432
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.755066 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.999830 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.999967 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.999715 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.999943 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.755062 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999773 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999955 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030580 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755064 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.645070
|
||||
system.ruby.network.routers2.msg_count.Control::2 97760
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000270 # Number of seconds simulated
|
||||
sim_ticks 270200000 # Number of ticks simulated
|
||||
final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 269998000 # Number of ticks simulated
|
||||
final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24805 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24804 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29619482 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244928 # Number of bytes of host memory used
|
||||
host_seconds 9.12 # Real time elapsed on the host
|
||||
host_inst_rate 216821 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 216819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 258712153 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263004 # Number of bytes of host memory used
|
||||
host_seconds 1.04 # Real time elapsed on the host
|
||||
sim_insts 226275 # Number of instructions simulated
|
||||
sim_ops 226275 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 86336 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 67072 # Nu
|
|||
system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1349 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 269959000 # Total gap between requests
|
||||
system.physmem.totGap 269757000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::62 0 # Wh
|
|||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 15283750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 15217250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 2.50 # Data bus utilization in percentage
|
||||
|
|
@ -221,59 +221,59 @@ system.physmem.readRowHits 1101 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 200117.87 # Average gap between requests
|
||||
system.physmem.avgGap 199968.12 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 548.697113 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states
|
||||
system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 549.494877 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states
|
||||
system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 540.858753 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 541.901675 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 61485 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 29457 # Number of BTB hits
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 61459 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 29463 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -295,16 +295,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 115 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 540400 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 539996 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 226275 # Number of instructions committed
|
||||
system.cpu.committedOps 226275 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 2.388244 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.418718 # IPC: instructions per cycle
|
||||
system.cpu.cpi 2.386459 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.419031 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction
|
||||
|
|
@ -344,34 +344,34 @@ system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 226275 # Class of committed instruction
|
||||
system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 90015 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 90016 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses
|
||||
|
|
@ -380,22 +380,22 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n
|
|||
system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 499 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses
|
||||
|
|
@ -404,14 +404,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005513
|
|||
system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -434,84 +434,84 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 302
|
|||
system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 69 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 206597 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 101722 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 206433 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 101640 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1051 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -526,36 +526,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1051
|
|||
system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
|
||||
|
|
@ -563,7 +563,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
||||
|
|
@ -590,16 +590,16 @@ system.cpu.l2cache.overall_misses::cpu.data 301 #
|
|||
system.cpu.l2cache.overall_misses::total 1349 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -628,16 +628,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 301
|
|||
system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -682,23 +682,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
|
||||
|
|
@ -736,7 +736,7 @@ system.membus.snoop_filter.hit_multi_requests 0
|
|||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1144 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 205 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 205 # Transaction distribution
|
||||
|
|
@ -757,9 +757,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1349 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 2.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.004665 # Nu
|
|||
sim_ticks 4665394 # Number of ticks simulated
|
||||
final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17585 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17585 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 362753 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412420 # Number of bytes of host memory used
|
||||
host_seconds 12.86 # Real time elapsed on the host
|
||||
host_inst_rate 87650 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87650 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1808106 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429644 # Number of bytes of host memory used
|
||||
host_seconds 2.58 # Real time elapsed on the host
|
||||
sim_insts 226159 # Number of instructions simulated
|
||||
sim_ops 226159 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.140999
|
|||
system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 72247
|
||||
system.ruby.Directory.incomplete_times_seqr 72246
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999904 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751856 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999322 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.067565 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061941 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999887 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999420 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999905 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092910 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751873 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.742647
|
||||
system.ruby.network.routers0.msg_count.Control::2 72247
|
||||
|
|
@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 577976
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 5201496
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751860 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999808 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999970 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.742647
|
||||
system.ruby.network.routers1.msg_count.Control::2 72247
|
||||
|
|
@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 577976
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 5201496
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.751870 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.999712 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.999954 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.999518 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.999922 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.751864 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999615 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999938 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030971 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751867 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 7.742647
|
||||
system.ruby.network.routers2.msg_count.Control::2 72247
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000165 # Nu
|
|||
sim_ticks 165091500 # Number of ticks simulated
|
||||
final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30601 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30601 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44574860 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244264 # Number of bytes of host memory used
|
||||
host_seconds 3.70 # Real time elapsed on the host
|
||||
host_inst_rate 261359 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 380682439 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261856 # Number of bytes of host memory used
|
||||
host_seconds 0.43 # Real time elapsed on the host
|
||||
sim_insts 113337 # Number of instructions simulated
|
||||
sim_ops 113337 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # By
|
|||
system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 16657750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 16727250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -229,19 +229,19 @@ system.physmem_0.readEnergy 3348660 # En
|
|||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 555.739358 # Core power per rank (mW)
|
||||
system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 555.750261 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states
|
||||
system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ)
|
||||
|
|
@ -249,31 +249,31 @@ system.physmem_1.writeEnergy 0 # En
|
|||
system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 547.349607 # Core power per rank (mW)
|
||||
system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 547.351788 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 31704 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15332 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 31695 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15330 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -301,7 +301,7 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 113337 # Number of instructions committed
|
||||
system.cpu.committedOps 113337 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 2.913285 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.343255 # IPC: instructions per cycle
|
||||
|
|
@ -344,16 +344,16 @@ system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 113337 # Class of committed instruction
|
||||
system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id
|
||||
|
|
@ -361,17 +361,17 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 4
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 43868 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 43871 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
|
||||
|
|
@ -380,38 +380,38 @@ system.cpu.dcache.demand_misses::cpu.data 453 # n
|
|||
system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 453 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -434,14 +434,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 263
|
|||
system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -450,68 +450,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 101777 # Number of data accesses
|
||||
system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 101683 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49717 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 49670 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 781 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -526,33 +526,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 781
|
|||
system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy
|
||||
|
|
@ -586,16 +586,16 @@ system.cpu.l2cache.overall_misses::cpu.data 262 #
|
|||
system.cpu.l2cache.overall_misses::total 1043 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -624,16 +624,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -654,16 +654,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 262
|
|||
system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -678,16 +678,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -753,9 +753,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1043 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.001842 # Nu
|
|||
sim_ticks 1841805 # Number of ticks simulated
|
||||
final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30529 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30529 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 496310 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411128 # Number of bytes of host memory used
|
||||
host_seconds 3.71 # Real time elapsed on the host
|
||||
host_inst_rate 106701 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 106700 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1734637 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 428500 # Number of bytes of host memory used
|
||||
host_seconds 1.06 # Real time elapsed on the host
|
||||
sim_insts 113291 # Number of instructions simulated
|
||||
sim_ops 113291 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -402,13 +402,35 @@ system.ruby.miss_latency_hist_seqr::stdev 34.809845
|
|||
system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 29717
|
||||
system.ruby.Directory.incomplete_times_seqr 29716
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999752 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.740878 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998244 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.085150 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.064534 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999715 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998498 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999759 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.096797 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.740922 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 8.066815
|
||||
system.ruby.network.routers0.msg_count.Control::2 29717
|
||||
|
|
@ -419,6 +441,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 237736
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 2139336
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.740889 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999504 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999924 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 8.066815
|
||||
system.ruby.network.routers1.msg_count.Control::2 29717
|
||||
|
|
@ -429,6 +457,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 237736
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 2139336
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 7.740915 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 2.999254 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.999884 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 4.998751 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.999802 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 9.740899 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999003 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.016135 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999844 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.032267 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.740908 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 8.066815
|
||||
system.ruby.network.routers2.msg_count.Control::2 29717
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000014 # Nu
|
|||
sim_ticks 13821 # Number of ticks simulated
|
||||
final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 213268 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 483832 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 253620 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 491252 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -332,11 +332,23 @@ system.cp_cntrl0.L2cache.num_data_array_reads 81
|
|||
system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes
|
||||
system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads
|
||||
system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes
|
||||
system.cp_cntrl0.mandatoryQueue.avg_buf_msgs 25.716177 # Average number of messages in buffer
|
||||
system.cp_cntrl0.mandatoryQueue.avg_stall_time 2962.798293 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.probeToCore.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.cp_cntrl0.probeToCore.avg_stall_time 33.503111 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.requestFromCore.avg_buf_msgs 0.169512 # Average number of messages in buffer
|
||||
system.cp_cntrl0.requestFromCore.avg_stall_time 14.915352 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.responseFromCore.avg_buf_msgs 0.311460 # Average number of messages in buffer
|
||||
system.cp_cntrl0.responseFromCore.avg_stall_time 14.764506 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.responseToCore.avg_buf_msgs 0.011069 # Average number of messages in buffer
|
||||
system.cp_cntrl0.responseToCore.avg_stall_time 14.645999 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
|
||||
system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store
|
||||
system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store
|
||||
system.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.088699 # Average number of messages in buffer
|
||||
system.cp_cntrl0.unblockFromCore.avg_stall_time 14.634279 # Average number of cycles messages are stalled in this MB
|
||||
system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
|
|
@ -347,7 +359,38 @@ system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372
|
|||
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes
|
||||
system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array
|
||||
system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array
|
||||
system.dir_cntrl0.L3triggerQueue.avg_buf_msgs 0.048835 # Average number of messages in buffer
|
||||
system.dir_cntrl0.L3triggerQueue.avg_stall_time 12.961945 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.probeToCore.avg_buf_msgs 0.653306 # Average number of messages in buffer
|
||||
system.dir_cntrl0.probeToCore.avg_stall_time 29.756909 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.requestFromCores.avg_buf_msgs 4.168499 # Average number of messages in buffer
|
||||
system.dir_cntrl0.requestFromCores.avg_stall_time 219.183837 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.requestFromCores.num_msg_stalls 6 # Number of times messages were stalled
|
||||
system.dir_cntrl0.responseFromCores.avg_buf_msgs 0.236001 # Average number of messages in buffer
|
||||
system.dir_cntrl0.responseFromCores.avg_stall_time 44.490812 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.033280 # Average number of messages in buffer
|
||||
system.dir_cntrl0.responseFromMemory.avg_stall_time 1.594198 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.responseToCore.avg_buf_msgs 0.651932 # Average number of messages in buffer
|
||||
system.dir_cntrl0.responseToCore.avg_stall_time 21.888945 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.triggerQueue.avg_buf_msgs 0.808711 # Average number of messages in buffer
|
||||
system.dir_cntrl0.triggerQueue.avg_stall_time 28.172406 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.021343 # Average number of messages in buffer
|
||||
system.dir_cntrl0.unblockFromCores.avg_stall_time 89.749240 # Average number of cycles messages are stalled in this MB
|
||||
system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.ext_links00.int_node.port_buffers000.avg_buf_msgs 0.026914 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers000.avg_stall_time 83.794892 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers002.avg_buf_msgs 0.026697 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers002.avg_stall_time 39.227029 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers004.avg_buf_msgs 0.021343 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers004.avg_stall_time 88.782810 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers005.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers005.avg_stall_time 30.553683 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers007.avg_buf_msgs 0.011069 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers007.avg_stall_time 11.722616 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers015.avg_buf_msgs 0.006077 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers015.avg_stall_time 30.746563 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.port_buffers017.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links00.int_node.port_buffers017.avg_stall_time 30.419114 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915
|
||||
system.ruby.network.ext_links00.int_node.msg_count.Control::0 300
|
||||
|
|
@ -364,6 +407,16 @@ system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1
|
|||
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824
|
||||
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568
|
||||
system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360
|
||||
system.ruby.network.ext_links01.int_node.port_buffers000.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links01.int_node.port_buffers000.avg_stall_time 32.520113 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links01.int_node.port_buffers002.avg_buf_msgs 0.011069 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links01.int_node.port_buffers002.avg_stall_time 13.671683 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links01.int_node.port_buffers003.avg_buf_msgs 0.011214 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links01.int_node.port_buffers003.avg_stall_time 15.908552 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links01.int_node.port_buffers005.avg_buf_msgs 0.020764 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links01.int_node.port_buffers005.avg_stall_time 15.747649 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links01.int_node.port_buffers007.avg_buf_msgs 0.005860 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links01.int_node.port_buffers007.avg_stall_time 15.608740 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680
|
||||
system.ruby.network.ext_links01.int_node.msg_count.Control::0 216
|
||||
|
|
@ -405,8 +458,76 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.009767 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.mandatoryQueue.avg_stall_time 1.140790 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.007741 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.probeToTCP.avg_stall_time 6.886268 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.308928 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.requestFromTCP.avg_stall_time 39.646940 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.289249 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.responseFromTCP.avg_stall_time 38.260744 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.007597 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.responseToTCP.avg_stall_time 2.919621 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer
|
||||
system.tcp_cntrl0.unblockFromCore.avg_stall_time 38.422804 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.ext_links02.int_node.port_buffers001.avg_buf_msgs 0.007235 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers001.avg_stall_time 5.756909 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers003.avg_buf_msgs 0.007452 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers003.avg_stall_time 1.927073 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers005.avg_buf_msgs 0.007018 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers005.avg_stall_time 5.309796 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers007.avg_buf_msgs 0.007018 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers007.avg_stall_time 1.940095 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers009.avg_buf_msgs 0.006656 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers009.avg_stall_time 5.861091 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers011.avg_buf_msgs 0.006945 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers011.avg_stall_time 1.961800 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers013.avg_buf_msgs 0.006222 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers013.avg_stall_time 5.483432 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers015.avg_buf_msgs 0.006367 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers015.avg_stall_time 1.879323 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers017.avg_buf_msgs 0.007524 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers017.avg_stall_time 5.492114 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers019.avg_buf_msgs 0.007452 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers019.avg_stall_time 1.931414 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers021.avg_buf_msgs 0.006367 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers021.avg_stall_time 5.539864 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers023.avg_buf_msgs 0.006656 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers023.avg_stall_time 1.957459 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers025.avg_buf_msgs 0.008031 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers025.avg_stall_time 5.544205 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers027.avg_buf_msgs 0.008320 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers027.avg_stall_time 1.947041 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers029.avg_buf_msgs 0.006439 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers029.avg_stall_time 5.457387 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers031.avg_buf_msgs 0.006728 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers031.avg_stall_time 1.901027 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers036.avg_buf_msgs 0.006077 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers036.avg_stall_time 32.725438 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers037.avg_buf_msgs 0.059543 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers037.avg_stall_time 41.896903 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers038.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers038.avg_stall_time 32.376863 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers039.avg_buf_msgs 0.056794 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers039.avg_stall_time 40.742295 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers041.avg_buf_msgs 0.058602 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers041.avg_stall_time 41.125452 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers043.avg_buf_msgs 0.000796 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers043.avg_stall_time 2.867168 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers045.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers045.avg_stall_time 1.317610 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers047.avg_buf_msgs 0.000796 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers047.avg_stall_time 3.139343 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers049.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers049.avg_stall_time 1.151208 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers050.avg_buf_msgs 0.015700 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers050.avg_stall_time 119.555564 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers052.avg_buf_msgs 0.005933 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers052.avg_stall_time 118.925264 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.port_buffers054.avg_buf_msgs 0.015483 # Average number of messages in buffer
|
||||
system.ruby.network.ext_links02.int_node.port_buffers054.avg_stall_time 117.253220 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944
|
||||
system.ruby.network.ext_links02.int_node.msg_count.Control::0 84
|
||||
|
|
@ -454,7 +575,19 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.010491 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.mandatoryQueue.avg_stall_time 1.432571 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.007524 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.probeToTCP.avg_stall_time 6.242584 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.289394 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.requestFromTCP.avg_stall_time 39.762697 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.responseFromTCP.avg_stall_time 35.279988 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.007235 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.responseToTCP.avg_stall_time 2.914484 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.280712 # Average number of messages in buffer
|
||||
system.tcp_cntrl1.unblockFromCore.avg_stall_time 38.683259 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -481,7 +614,19 @@ system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl2.mandatoryQueue.avg_buf_msgs 0.010418 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.mandatoryQueue.avg_stall_time 1.277312 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.probeToTCP.avg_stall_time 6.844596 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.requestFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.requestFromTCP.avg_stall_time 39.878455 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.responseFromTCP.avg_buf_msgs 0.266242 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.responseFromTCP.avg_stall_time 38.955289 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.responseToTCP.avg_buf_msgs 0.007307 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.responseToTCP.avg_stall_time 2.965417 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl2.unblockFromCore.avg_buf_msgs 0.277818 # Average number of messages in buffer
|
||||
system.tcp_cntrl2.unblockFromCore.avg_stall_time 39.117349 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -509,7 +654,19 @@ system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl3.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.mandatoryQueue.avg_stall_time 1.170164 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.probeToTCP.avg_stall_time 6.502170 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.requestFromTCP.avg_buf_msgs 0.261684 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.requestFromTCP.avg_stall_time 39.039213 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.responseFromTCP.avg_buf_msgs 0.247504 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.responseFromTCP.avg_stall_time 36.437563 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.responseToTCP.avg_stall_time 2.855954 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl3.unblockFromCore.avg_buf_msgs 0.254666 # Average number of messages in buffer
|
||||
system.tcp_cntrl3.unblockFromCore.avg_stall_time 37.467805 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -537,7 +694,19 @@ system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl4.mandatoryQueue.avg_buf_msgs 0.009478 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.mandatoryQueue.avg_stall_time 1.107365 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.probeToTCP.avg_buf_msgs 0.008031 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.probeToTCP.avg_stall_time 6.466141 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.requestFromTCP.avg_buf_msgs 0.298076 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.requestFromTCP.avg_stall_time 39.733758 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.responseFromTCP.avg_buf_msgs 0.300969 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.responseFromTCP.avg_stall_time 36.495442 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.responseToTCP.avg_buf_msgs 0.008175 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.responseToTCP.avg_stall_time 2.934380 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl4.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer
|
||||
system.tcp_cntrl4.unblockFromCore.avg_stall_time 38.509622 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -564,7 +733,19 @@ system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl5.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.mandatoryQueue.avg_stall_time 1.079728 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.probeToTCP.avg_stall_time 6.478585 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.requestFromTCP.avg_buf_msgs 0.269136 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.requestFromTCP.avg_stall_time 39.849515 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.responseFromTCP.avg_buf_msgs 0.254015 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.responseFromTCP.avg_stall_time 36.813775 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.responseToTCP.avg_buf_msgs 0.006945 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.responseToTCP.avg_stall_time 2.959991 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl5.unblockFromCore.avg_buf_msgs 0.266242 # Average number of messages in buffer
|
||||
system.tcp_cntrl5.unblockFromCore.avg_stall_time 39.030531 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -591,7 +772,19 @@ system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl6.mandatoryQueue.avg_buf_msgs 0.010201 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.mandatoryQueue.avg_stall_time 1.122414 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.probeToTCP.avg_buf_msgs 0.009405 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.probeToTCP.avg_stall_time 6.666763 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.requestFromTCP.avg_buf_msgs 0.335697 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.requestFromTCP.avg_stall_time 39.618000 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.responseFromTCP.avg_buf_msgs 0.321227 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.responseFromTCP.avg_stall_time 36.842715 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.responseToTCP.avg_buf_msgs 0.008682 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.responseToTCP.avg_stall_time 2.959051 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl6.unblockFromCore.avg_buf_msgs 0.331718 # Average number of messages in buffer
|
||||
system.tcp_cntrl6.unblockFromCore.avg_stall_time 38.822168 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -618,7 +811,19 @@ system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 #
|
|||
system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
|
||||
system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
|
||||
system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU
|
||||
system.tcp_cntrl7.mandatoryQueue.avg_buf_msgs 0.008103 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.mandatoryQueue.avg_stall_time 1.097743 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.probeToTCP.avg_stall_time 6.394371 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.requestFromTCP.avg_buf_msgs 0.272030 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.requestFromTCP.avg_stall_time 39.357546 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.responseFromTCP.avg_buf_msgs 0.254739 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.responseFromTCP.avg_stall_time 36.263927 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.responseToTCP.avg_stall_time 2.863696 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcp_cntrl7.unblockFromCore.avg_buf_msgs 0.269136 # Average number of messages in buffer
|
||||
system.tcp_cntrl7.unblockFromCore.avg_stall_time 37.901896 # Average number of cycles messages are stalled in this MB
|
||||
system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -627,7 +832,19 @@ system.sqc_cntrl0.L1cache.num_data_array_reads 12
|
|||
system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes
|
||||
system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads
|
||||
system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes
|
||||
system.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.mandatoryQueue.avg_stall_time 0.668499 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.probeToSQC.avg_stall_time 3.344523 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.requestFromSQC.avg_stall_time 53.016930 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.responseFromSQC.avg_stall_time 37.760093 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.responseToSQC.avg_stall_time 1.976197 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer
|
||||
system.sqc_cntrl0.unblockFromCore.avg_stall_time 52.235566 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
|
||||
system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -636,7 +853,19 @@ system.sqc_cntrl1.L1cache.num_data_array_reads 12
|
|||
system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes
|
||||
system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads
|
||||
system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes
|
||||
system.sqc_cntrl1.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.mandatoryQueue.avg_stall_time 0.585299 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.probeToSQC.avg_stall_time 3.662060 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.requestFromSQC.avg_stall_time 46.360874 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.responseFromSQC.avg_stall_time 41.389090 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.responseToSQC.avg_stall_time 1.726595 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.sqc_cntrl1.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer
|
||||
system.sqc_cntrl1.unblockFromCore.avg_stall_time 45.579511 # Average number of cycles messages are stalled in this MB
|
||||
system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
|
||||
system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
|
||||
|
|
@ -647,7 +876,49 @@ system.tccdir_cntrl0.directory.demand_misses 0
|
|||
system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
|
||||
system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads
|
||||
system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes
|
||||
system.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.035740 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.probeFromNB.avg_stall_time 35.754884 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.265157 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.probeToCore.avg_stall_time 4.884604 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 1.395239 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.requestFromTCP.avg_stall_time 55.396180 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.requestToNB.avg_buf_msgs 1.900159 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.requestToNB.avg_stall_time 118.576183 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.responseFromNB.avg_stall_time 33.355520 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.056794 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.responseFromTCP.avg_stall_time 41.713066 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.058602 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.responseToCore.avg_stall_time 0.980972 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.718203 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.responseToNB.avg_stall_time 117.951092 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.052814 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.triggerQueue.avg_stall_time 0.973665 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.058602 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.unblockFromTCP.avg_stall_time 42.100275 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.unblockToNB.avg_buf_msgs 1.864274 # Average number of messages in buffer
|
||||
system.tccdir_cntrl0.unblockToNB.avg_stall_time 116.292866 # Average number of cycles messages are stalled in this MB
|
||||
system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.int_link_buffers00.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers00.avg_stall_time 31.536970 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.011069 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 12.697222 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers10.avg_buf_msgs 0.006077 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers10.avg_stall_time 31.736073 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers12.avg_buf_msgs 0.015627 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers12.avg_stall_time 31.398061 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers20.avg_buf_msgs 0.011214 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers20.avg_stall_time 16.901606 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers22.avg_buf_msgs 0.020764 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers22.avg_stall_time 16.730647 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers24.avg_buf_msgs 0.005860 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers24.avg_stall_time 16.583056 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers30.avg_buf_msgs 0.015700 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers30.avg_stall_time 120.534800 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers32.avg_buf_msgs 0.005933 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers32.avg_stall_time 119.899291 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015483 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers34.avg_stall_time 118.213428 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.msg_count.Control 1389
|
||||
system.ruby.network.msg_count.Request_Control 1567
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ sim_seconds 0.000044 # Nu
|
|||
sim_ticks 44021 # Number of ticks simulated
|
||||
final_tick 44021 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 728057 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409368 # Number of bytes of host memory used
|
||||
host_tick_rate 749300 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 393900 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
|
|
@ -314,6 +314,14 @@ system.ruby.miss_latency_hist_seqr::gmean 665.813242
|
|||
system.ruby.miss_latency_hist_seqr::stdev 238.941361
|
||||
system.ruby.miss_latency_hist_seqr | 54 5.98% 5.98% | 28 3.10% 9.08% | 4 0.44% 9.52% | 3 0.33% 9.86% | 6 0.66% 10.52% | 263 29.13% 39.65% | 367 40.64% 80.29% | 113 12.51% 92.80% | 53 5.87% 98.67% | 12 1.33% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 903
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.019672 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.800736 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.039208 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998319 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.037345 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998342 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.019581 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.079642 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 101 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 855 # Number of cache demand misses
|
||||
|
|
@ -321,6 +329,9 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 956
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.866976 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 7.367248 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 11024 # Number of times messages were stalled
|
||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
|
|
@ -330,16 +341,49 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.077552 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999818 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 6.577348 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.012176 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.879151 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.038731 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.395552 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.unblockFromL1Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.unblockFromL1Cache.avg_stall_time 0.998001 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_buf_msgs 0.039344 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_stall_time 1.999455 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.006201 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 0.939757 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.394962 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 24.096134 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.num_msg_stalls 396 # Number of times messages were stalled
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 905 # Number of cache demand accesses
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.078756 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.598428 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.045273 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.165917 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.unblockToL2Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.unblockToL2Cache.avg_stall_time 6.985053 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers01.avg_stall_time 7.397778 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers02.avg_stall_time 5.637863 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.204034 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 11.022807 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.006542 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 2.850416 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers05.avg_stall_time 1.995957 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 11.308239
|
||||
system.ruby.network.routers0.msg_count.Control::0 905
|
||||
|
|
@ -358,6 +402,18 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6816
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 55368
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15696
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 264
|
||||
system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers00.avg_stall_time 15.044228 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.045273 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers01.avg_stall_time 6.167871 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 5.987325 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.099337 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers03.avg_stall_time 6.730339 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.085185 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers04.avg_stall_time 2.717936 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers05.avg_stall_time 1.879469 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 20.738398
|
||||
system.ruby.network.routers1.msg_count.Control::0 1771
|
||||
|
|
@ -376,6 +432,12 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6816
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 55368
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15696
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 264
|
||||
system.ruby.network.routers2.port_buffers00.avg_buf_msgs 0.019672 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers00.avg_stall_time 10.801508 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.019581 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers01.avg_stall_time 7.082459 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.041570 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 2.061628 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 9.432430
|
||||
system.ruby.network.routers2.msg_count.Control::0 866
|
||||
|
|
@ -384,6 +446,48 @@ system.ruby.network.routers2.msg_count.Response_Control::1 943
|
|||
system.ruby.network.routers2.msg_bytes.Control::0 6928
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 118440
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 7544
|
||||
system.ruby.network.int_link_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers00.avg_stall_time 12.022534 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers01.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers01.avg_stall_time 3.789878 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 2.993867 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers03.avg_buf_msgs 0.019672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers03.avg_stall_time 7.729749 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers04.avg_buf_msgs 0.058312 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers04.avg_stall_time 3.715892 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers05.avg_stall_time 2.819136 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers07.avg_buf_msgs 0.039208 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers07.avg_stall_time 3.059856 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers10.avg_buf_msgs 0.038731 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers10.avg_stall_time 6.399959 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers11.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers11.avg_stall_time 4.698333 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers12.avg_buf_msgs 0.038776 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers12.avg_stall_time 14.044637 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.045273 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 5.169779 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.989551 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers15.avg_buf_msgs 0.019672 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers15.avg_stall_time 9.802235 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers16.avg_buf_msgs 0.019581 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers16.avg_stall_time 6.085230 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers01.avg_stall_time 5.402094 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers02.avg_stall_time 3.758757 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.039094 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers03.avg_stall_time 13.045000 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.046045 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers04.avg_stall_time 4.171641 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers05.avg_stall_time 3.991731 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers06.avg_buf_msgs 0.021171 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers06.avg_stall_time 8.802917 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.019581 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers07.avg_stall_time 5.087956 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers3.percent_links_utilized 13.825598
|
||||
system.ruby.network.routers3.msg_count.Control::0 1771
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000057 # Nu
|
|||
sim_ticks 57351 # Number of ticks simulated
|
||||
final_tick 57351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 527309 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410220 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 566783 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 396800 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -311,6 +311,16 @@ system.ruby.miss_latency_hist_seqr::gmean 881.514808
|
|||
system.ruby.miss_latency_hist_seqr::stdev 261.625282
|
||||
system.ruby.miss_latency_hist_seqr | 55 6.05% 6.05% | 9 0.99% 7.04% | 4 0.44% 7.48% | 380 41.80% 49.28% | 412 45.32% 94.61% | 49 5.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 909
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.082752 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 5.967569 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 8.096701 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015361 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998710 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998727 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.029136 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.057888 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 88 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses
|
||||
|
|
@ -318,16 +328,50 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 947
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 52 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.523364 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 864.375262 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999861 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.015762 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 8.191536 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.996792 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.015849 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.002040 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 89 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.014263 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 0.998431 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.058307 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 1.999582 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_buf_msgs 0.013792 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_stall_time 12.105995 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.031525 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 1.994699 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.031612 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 8.273016 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 28 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 881 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 909 # Number of cache demand accesses
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.089971 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.997106 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.046956 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.981239 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.triggerQueue.avg_buf_msgs 0.013879 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.triggerQueue.avg_stall_time 0.998588 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers00.avg_stall_time 7.194431 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers02.avg_stall_time 7.003714 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.035622 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 3.255039 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.034628 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers05.avg_stall_time 3.156385 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 8.691653
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 909
|
||||
|
|
@ -342,6 +386,18 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2016
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65088
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14464
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7264
|
||||
system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers00.avg_stall_time 7.273312 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.013792 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers01.avg_stall_time 11.111696 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.046956 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 6.982738 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.019127 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers03.avg_stall_time 3.205660 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.030740 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers04.avg_stall_time 3.098532 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.048542 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers05.avg_stall_time 3.049118 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 16.709822
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 909
|
||||
|
|
@ -360,6 +416,14 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 122040
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14464
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12656
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14304
|
||||
system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers01.avg_stall_time 7.097137 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.029136 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers02.avg_stall_time 7.059858 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014891 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 7.047653 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers05.avg_buf_msgs 0.016006 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers05.avg_stall_time 2.063241 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 8.016861
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 881
|
||||
|
|
@ -372,6 +436,48 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 63432
|
|||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56952
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12656
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 7040
|
||||
system.ruby.network.int_link_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers00.avg_stall_time 4.254882 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031594 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 4.154694 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers03.avg_buf_msgs 0.015762 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers03.avg_stall_time 4.202905 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers04.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers04.avg_stall_time 4.098235 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers05.avg_buf_msgs 0.044985 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers05.avg_stall_time 4.047583 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers07.avg_buf_msgs 0.013792 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers07.avg_stall_time 8.042091 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015361 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 3.061881 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015762 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 6.197290 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers11.avg_buf_msgs 0.015849 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers11.avg_stall_time 6.005353 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers12.avg_buf_msgs 0.031612 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers12.avg_stall_time 6.273574 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013792 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 10.117363 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.046956 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 5.984203 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers16.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers16.avg_stall_time 6.097538 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029136 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 6.061794 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers00.avg_stall_time 5.200115 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers02.avg_stall_time 5.006957 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.032030 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers03.avg_stall_time 5.273800 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.017140 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers04.avg_stall_time 9.122995 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.050792 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers05.avg_stall_time 4.985633 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.029153 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers07.avg_stall_time 5.097904 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers08.avg_buf_msgs 0.029136 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers08.avg_stall_time 5.063694 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers3.percent_links_utilized 11.139881
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 909
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu
|
|||
sim_ticks 53801 # Number of ticks simulated
|
||||
final_tick 53801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 784976 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409916 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 1148907 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 394184 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -310,6 +310,16 @@ system.ruby.miss_latency_hist_seqr::stdev 300.791358
|
|||
system.ruby.miss_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 822
|
||||
system.ruby.Directory.incomplete_times_seqr 822
|
||||
system.ruby.dir_cntrl0.persistentToDir.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.persistentToDir.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.015334 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.130237 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015297 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998569 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029107 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998587 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.015204 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseToDir.avg_stall_time 10.935597 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 92 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 820 # Number of cache demand misses
|
||||
|
|
@ -317,16 +327,49 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 912
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.571763 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 24.837199 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 22280 # Number of times messages were stalled
|
||||
system.ruby.l1_cntrl0.persistentFromL1Cache.avg_buf_msgs 0.001413 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.persistentFromL1Cache.avg_stall_time 1.410728 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.persistentToL1Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.persistentToL1Cache.avg_stall_time 2.822237 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.064533 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999851 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.032285 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.976135 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.016356 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 7.201145 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 91 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.076670 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 4.998606 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 12.070443 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 825 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 868 # Number of cache demand accesses
|
||||
system.ruby.l2_cntrl0.persistentToL2Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.persistentToL2Cache.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.079142 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 4.970763 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.016022 # Average number of messages in buffer
|
||||
system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 8.050407 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.000725 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 2.116966 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016356 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 6.202799 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers06.avg_buf_msgs 0.081800 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers06.avg_stall_time 7.012881 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers08.avg_buf_msgs 0.001673 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers08.avg_stall_time 3.678283 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers09.avg_buf_msgs 0.016932 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers09.avg_stall_time 3.044943 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 7.774948
|
||||
system.ruby.network.routers0.msg_count.Request_Control::1 868
|
||||
|
|
@ -339,6 +382,16 @@ system.ruby.network.routers0.msg_bytes.Response_Data::4 59256
|
|||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3168
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 63936
|
||||
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 608
|
||||
system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers01.avg_stall_time 11.070834 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.016022 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers04.avg_stall_time 7.053158 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016747 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 6.087710 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.016672 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers09.avg_stall_time 6.054478 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 7.735451
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 868
|
||||
|
|
@ -353,6 +406,14 @@ system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3168
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 115560
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 600
|
||||
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 304
|
||||
system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.015334 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers02.avg_stall_time 10.130813 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015204 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 9.940969 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers09.avg_buf_msgs 0.015576 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers09.avg_stall_time 2.034924 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 6.985000
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 825
|
||||
|
|
@ -365,6 +426,46 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 59256
|
|||
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 53496
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 600
|
||||
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 304
|
||||
system.ruby.network.int_link_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers01.avg_stall_time 8.012639 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers03.avg_stall_time 4.383480 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers04.avg_buf_msgs 0.016263 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers04.avg_stall_time 4.042340 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015334 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 7.087283 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers10.avg_stall_time 7.049255 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers16.avg_buf_msgs 0.015297 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers16.avg_stall_time 3.033419 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers22.avg_buf_msgs 0.016356 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers22.avg_stall_time 5.204416 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers25.avg_buf_msgs 0.016133 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers25.avg_stall_time 10.071187 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers27.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers27.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers28.avg_buf_msgs 0.016022 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers28.avg_stall_time 6.055872 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers32.avg_buf_msgs 0.015334 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers32.avg_stall_time 9.131352 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers33.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers33.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015204 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers34.avg_stall_time 8.946303 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.016449 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers04.avg_stall_time 4.205996 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.017063 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers07.avg_stall_time 9.071503 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers09.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers09.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers10.avg_stall_time 5.058548 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers14.avg_buf_msgs 0.015947 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers14.avg_stall_time 8.131854 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers15.avg_buf_msgs 0.000706 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers15.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.port_buffers16.avg_buf_msgs 0.015464 # Average number of messages in buffer
|
||||
system.ruby.network.routers3.port_buffers16.avg_stall_time 7.951600 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers3.percent_links_utilized 7.498621
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 868
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000031 # Nu
|
|||
sim_ticks 31071 # Number of ticks simulated
|
||||
final_tick 31071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 307258 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409592 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 718641 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 392596 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -308,9 +308,20 @@ system.ruby.miss_latency_hist_seqr::stdev 216.457686
|
|||
system.ruby.miss_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 860
|
||||
system.ruby.Directory.incomplete_times_seqr 860
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.055098 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 1.993950 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.079332 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 9.743402 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.num_msg_stalls 247 # Number of times messages were stalled
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997779 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.052877 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997812 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.unblockToDir.avg_buf_msgs 0.055098 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.unblockToDir.avg_stall_time 16.445417 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 79 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
|
||||
|
|
@ -321,13 +332,34 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 63
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 54 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.027549 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.992179 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.810859 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 11.674884 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 17591 # Number of times messages were stalled
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.110582 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999743 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 7.080072 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
|
||||
system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.045411 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 1.709803 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.unblockFromCache.avg_buf_msgs 0.551686 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.unblockFromCache.avg_stall_time 9.972322 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 6.995623 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 6.082679 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.063755 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 3.199504 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers10.avg_buf_msgs 0.069355 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers10.avg_stall_time 11.461992 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 14.722732
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 863
|
||||
|
|
@ -344,6 +376,14 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6840
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6848
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 568
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6872
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 7.197960 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers05.avg_stall_time 15.448861 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.027871 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers09.avg_stall_time 3.008754 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers10.avg_buf_msgs 0.029480 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers10.avg_stall_time 2.092463 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 14.717100
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 863
|
||||
|
|
@ -360,6 +400,30 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6840
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6848
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 568
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6872
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 4.199215 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers05.avg_stall_time 12.458805 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.027549 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 4.005568 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers10.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers10.avg_stall_time 3.090113 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers15.avg_buf_msgs 0.027549 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers15.avg_stall_time 5.999002 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers16.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers16.avg_stall_time 5.085221 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers20.avg_buf_msgs 0.055291 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers20.avg_stall_time 6.198442 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers23.avg_buf_msgs 0.055130 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers23.avg_stall_time 14.452240 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 5.002317 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 4.087700 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers08.avg_buf_msgs 0.055291 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers08.avg_stall_time 5.198861 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers11.avg_buf_msgs 0.055130 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers11.avg_stall_time 13.455555 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 14.720318
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 863
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ sim_seconds 0.000039 # Nu
|
|||
sim_ticks 39431 # Number of ticks simulated
|
||||
final_tick 39431 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 979592 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 407616 # Number of bytes of host memory used
|
||||
host_tick_rate 995299 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 392160 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
|
|
@ -315,16 +315,38 @@ system.ruby.miss_latency_hist_seqr::stdev 106.107284
|
|||
system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 940
|
||||
system.ruby.Directory.incomplete_times_seqr 940
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997388 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 16.301050 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.023864 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998250 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998276 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.382152 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.964749 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 523.362675 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.095303 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999797 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.023839 # Average number of messages in buffer
|
||||
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.986686 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers03.avg_stall_time 6.385068 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.023839 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.988740 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.261894 # Average number of messages in buffer
|
||||
system.ruby.network.routers0.port_buffers07.avg_stall_time 11.303840 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 11.905607
|
||||
system.ruby.network.routers0.msg_count.Control::2 941
|
||||
|
|
@ -335,6 +357,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 7528
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 67536
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 67680
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7504
|
||||
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers02.avg_stall_time 15.301709 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.029063 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers06.avg_stall_time 2.396226 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.023864 # Average number of messages in buffer
|
||||
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.996450 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 11.910045
|
||||
system.ruby.network.routers1.msg_count.Control::2 941
|
||||
|
|
@ -345,6 +373,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 7528
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 67536
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 67752
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7504
|
||||
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers02.avg_stall_time 12.303383 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers08.avg_stall_time 3.393513 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.023864 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers09.avg_stall_time 2.994598 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers13.avg_stall_time 5.387934 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.023839 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers14.avg_stall_time 4.990744 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.network.int_link_buffers17.avg_stall_time 14.302318 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers03.avg_stall_time 4.390749 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.023864 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.992696 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.047652 # Average number of messages in buffer
|
||||
system.ruby.network.routers2.port_buffers07.avg_stall_time 13.302876 # Average number of cycles messages are stalled in this MB
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 11.907509
|
||||
system.ruby.network.routers2.msg_count.Control::2 941
|
||||
|
|
|
|||
Loading…
Reference in a new issue