750 lines
86 KiB
Plaintext
750 lines
86 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.000014 # Number of seconds simulated
|
|
sim_ticks 14435000 # Number of ticks simulated
|
|
final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 136295 # Simulator instruction rate (inst/s)
|
|
host_op_rate 136181 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 1229999304 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 249560 # Number of bytes of host memory used
|
|
host_seconds 0.01 # Real time elapsed on the host
|
|
sim_insts 1597 # Number of instructions simulated
|
|
sim_ops 1597 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 12032 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 188 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 188 # Number of read requests accepted
|
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
|
system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 97 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 64 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 18 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 9 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 14206000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 188 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation
|
|
system.physmem.totQLat 1580250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 940000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 6.51 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 171 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
|
system.physmem.avgGap 75563.83 # Average gap between requests
|
|
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ)
|
|
system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 603.160028 # Core power per rank (mW)
|
|
system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states
|
|
system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 427.808105 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 995 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 100 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 11 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 191 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 9 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 28870 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 1597 # Number of instructions committed
|
|
system.cpu.committedOps 1597 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 18.077646 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.055317 # IPC: instructions per cycle
|
|
system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction
|
|
system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction
|
|
system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction
|
|
system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.op_class_0::total 1597 # Class of committed instruction
|
|
system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 645 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 44 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 1889 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 709 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 157 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181293 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.181293 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.181293 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.181293 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.181293 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.181293 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80003.184713 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 157 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12403500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12403500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 156 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 188 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 17 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 17 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 157 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 33 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993631 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993631 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.969697 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.989474 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993631 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.969697 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 78130.319149 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 171 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 17 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 17 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 188 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 188 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|