1715 lines
201 KiB
Plaintext
1715 lines
201 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 47.256223 # Number of seconds simulated
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sim_ticks 47256222864000 # Number of ticks simulated
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final_tick 47256222864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1686655 # Simulator instruction rate (inst/s)
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host_op_rate 2012712 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 87867845670 # Simulator tick rate (ticks/s)
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host_mem_usage 696856 # Number of bytes of host memory used
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host_seconds 537.81 # Real time elapsed on the host
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sim_insts 907100218 # Number of instructions simulated
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sim_ops 1082456754 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu0.dtb.walker 160064 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 126784 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 3921972 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 37880648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 245824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 244416 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 3131208 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 41316208 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 428544 # Number of bytes read from this memory
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system.physmem.bytes_read::total 87455668 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 3921972 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 3131208 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 7053180 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 106476736 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
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system.physmem.bytes_written::total 106497320 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 2501 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1981 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 65688 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 591898 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 3841 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 3819 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 49032 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 645582 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6696 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1371038 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1663699 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1666273 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 3387 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 2683 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 82994 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 801601 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 5202 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 5172 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 66260 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 874302 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 9069 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1850670 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 82994 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 66260 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 149254 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2253179 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2253615 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2253179 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 3387 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 2683 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 82994 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 802037 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 5202 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 5172 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 66260 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 874302 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 9069 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4104285 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
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system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.bridge.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.cpu0.dtb.walker.walks 130714 # Table walker walks requested
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system.cpu0.dtb.walker.walksLong 130714 # Table walker walks initiated with long descriptors
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system.cpu0.dtb.walker.walkWaitTime::samples 130714 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::0 130714 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::total 130714 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walkPageSizes::4K 100196 89.16% 89.16% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::2M 12181 10.84% 100.00% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::total 112377 # Table walker page sizes translated
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130714 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130714 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112377 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112377 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin::total 243091 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.read_hits 93175374 # DTB read hits
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system.cpu0.dtb.read_misses 92435 # DTB read misses
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system.cpu0.dtb.write_hits 86370526 # DTB write hits
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system.cpu0.dtb.write_misses 38279 # DTB write misses
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system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 36393 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 5252 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.perms_faults 10620 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.read_accesses 93267809 # DTB read accesses
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system.cpu0.dtb.write_accesses 86408805 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.hits 179545900 # DTB hits
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system.cpu0.dtb.misses 130714 # DTB misses
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system.cpu0.dtb.accesses 179676614 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
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system.cpu0.itb.walker.walks 60670 # Table walker walks requested
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system.cpu0.itb.walker.walksLong 60670 # Table walker walks initiated with long descriptors
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system.cpu0.itb.walker.walkWaitTime::samples 60670 # Table walker wait (enqueue to first request) latency
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|
system.cpu0.itb.walker.walkWaitTime::0 60670 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walkWaitTime::total 60670 # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution
|
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system.cpu0.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walkPageSizes::4K 54534 98.81% 98.81% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::2M 657 1.19% 100.00% # Table walker page sizes translated
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|
system.cpu0.itb.walker.walkPageSizes::total 55191 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60670 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60670 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55191 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55191 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 115861 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 460432126 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 60670 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 25186 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 460492796 # ITB inst accesses
|
|
system.cpu0.itb.hits 460432126 # DTB hits
|
|
system.cpu0.itb.misses 60670 # DTB misses
|
|
system.cpu0.itb.accesses 460492796 # DTB accesses
|
|
system.cpu0.numPwrStateTransitions 26581 # Number of power state transitions
|
|
system.cpu0.pwrStateClkGateDist::samples 13288 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::mean 3535659625.946418 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::stdev 88810636016.861053 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::underflows 3229 24.30% 24.30% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::1000-5e+10 10032 75.50% 99.80% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::max_value 7390911651500 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::total 13288 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateResidencyTicks::ON 274377754424 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46981845109576 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.numCycles 94512459022 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 13293 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 460154624 # Number of instructions committed
|
|
system.cpu0.committedOps 548413661 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 509180687 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 522850 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 28957516 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 67014933 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 509180687 # number of integer instructions
|
|
system.cpu0.num_fp_insts 522850 # number of float instructions
|
|
system.cpu0.num_int_register_reads 679939222 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 397756518 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 842282 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 446532 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 104721942 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 104390194 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 179652770 # number of memory refs
|
|
system.cpu0.num_load_insts 93252874 # Number of load instructions
|
|
system.cpu0.num_store_insts 86399896 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 93963703435.962769 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 548755586.037238 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.005806 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.994194 # Percentage of idle cycles
|
|
system.cpu0.Branches 101918794 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 367730477 67.01% 67.01% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 1235344 0.23% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 59786 0.01% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 8 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 13 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 21 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMultAcc 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMisc 72659 0.01% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 93191543 16.98% 84.24% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 86011078 15.67% 99.92% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMemRead 61331 0.01% 99.93% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMemWrite 388818 0.07% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 548751079 # Class of executed instruction
|
|
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.tags.replacements 6361267 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 499.577143 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 173125033 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 6361779 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 27.213305 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.577143 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975737 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.975737 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 365631383 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 365631383 # Number of data accesses
|
|
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 86603750 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 86603750 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 81517458 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 81517458 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 217950 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 217950 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259225 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::total 259225 # number of WriteLineReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2136353 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 2136353 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2100440 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 2100440 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 168380433 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 168380433 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 168598383 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 168598383 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 3343142 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 3343142 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1509525 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1509525 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 802963 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 802963 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 820079 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::total 820079 # number of WriteLineReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119939 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 119939 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154648 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 154648 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 5672746 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 5672746 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 6475709 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 6475709 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 89946892 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 89946892 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 83026983 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 83026983 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1020913 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 1020913 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1079304 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::total 1079304 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2256292 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 2256292 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2255088 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 2255088 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 174053179 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 174053179 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 175074092 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 175074092 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037168 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037168 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018181 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.018181 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786515 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786515 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759822 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759822 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053158 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053158 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068577 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068577 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032592 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.032592 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036988 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.036988 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 6361267 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 6361267 # number of writebacks
|
|
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.tags.replacements 5436488 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.989232 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 455050312 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 5437000 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 83.695110 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 5738328000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989232 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 926411639 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 926411639 # Number of data accesses
|
|
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 455050312 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 455050312 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 455050312 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 455050312 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 455050312 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 455050312 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 5437005 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 5437005 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 5437005 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 5437005 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 5437005 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 5437005 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 460487317 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 460487317 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 460487317 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 460487317 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 460487317 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 460487317 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011807 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011807 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011807 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011807 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011807 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011807 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 5436488 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 5436488 # number of writebacks
|
|
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.l2cache.tags.replacements 2619867 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 15716.053325 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 9431762 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 2635628 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 3.578563 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 269403000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 15665.638757 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.618352 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.796216 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.956155 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001869 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001208 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.959232 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15683 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2189 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5717 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5104 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.957214 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 403271236 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 403271236 # Number of data accesses
|
|
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 300949 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154418 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 455367 # number of ReadReq hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4541229 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::total 4541229 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackClean_hits::writebacks 7255159 # number of WritebackClean hits
|
|
system.cpu0.l2cache.WritebackClean_hits::total 7255159 # number of WritebackClean hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 644334 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 644334 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4939776 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::total 4939776 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3020372 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::total 3020372 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222433 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::total 222433 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 300949 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154418 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 4939776 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 3664706 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 9059849 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 300949 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154418 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 4939776 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 3664706 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 9059849 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21207 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 31327 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134662 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 134662 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154648 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 154648 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 730529 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 730529 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1245672 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::total 1245672 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597646 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::total 597646 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21207 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 1976201 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 2504757 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21207 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 1976201 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 2504757 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 322156 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164538 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 486694 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4541229 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::total 4541229 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7255159 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::total 7255159 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134662 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 134662 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154648 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 154648 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1374863 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 1374863 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5437005 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::total 5437005 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4266044 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::total 4266044 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 820079 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::total 820079 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 322156 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164538 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 5437005 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 5640907 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 11564606 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 322156 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164538 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 5437005 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 5640907 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 11564606 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061506 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.064367 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.531347 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.531347 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091453 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091453 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.291997 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.291997 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728766 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728766 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061506 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091453 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350334 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.216588 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061506 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091453 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350334 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.216588 # miss rate for overall accesses
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.writebacks::writebacks 1595934 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 1595934 # number of writebacks
|
|
system.cpu0.toL2Bus.snoop_filter.tot_requests 24251358 # Total number of requests made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12353916 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1372 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.tot_snoops 295344 # Total number of snoops made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 295344 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 597776 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 10300825 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 32321 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 32321 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackDirty 4541229 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackClean 7256526 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 134662 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154648 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 289310 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 1374863 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 1374863 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5437005 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4266044 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateReq 820079 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateResp 820079 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16319948 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19991301 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362448 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 758854 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 37432551 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 695922452 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 768331945 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1449792 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3035416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 1468739605 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 4809457 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoopTraffic 106507396 # Total snoop traffic (bytes)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 29250499 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 0.019295 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.137560 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 28686107 98.07% 98.07% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 564392 1.93% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 29250499 # Request fanout histogram
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dtb.walker.walks 149830 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksLong 149830 # Table walker walks initiated with long descriptors
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 149830 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 149830 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 149830 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -295973872 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 -295973872 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -295973872 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 115525 88.27% 88.27% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::2M 15355 11.73% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 130880 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 149830 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 149830 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 130880 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 130880 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 280710 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 93113840 # DTB read hits
|
|
system.cpu1.dtb.read_misses 115970 # DTB read misses
|
|
system.cpu1.dtb.write_hits 83725509 # DTB write hits
|
|
system.cpu1.dtb.write_misses 33860 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 45912 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 4582 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 11647 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 93229810 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 83759369 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 176839349 # DTB hits
|
|
system.cpu1.dtb.misses 149830 # DTB misses
|
|
system.cpu1.dtb.accesses 176989179 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.itb.walker.walks 62588 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksLong 62588 # Table walker walks initiated with long descriptors
|
|
system.cpu1.itb.walker.walkWaitTime::samples 62588 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 62588 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 62588 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walksPending::samples -295974872 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 -295974872 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total -295974872 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 55491 99.07% 99.07% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::2M 523 0.93% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 56014 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56014 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56014 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 118602 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 447202663 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 62588 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 32344 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 447265251 # ITB inst accesses
|
|
system.cpu1.itb.hits 447202663 # DTB hits
|
|
system.cpu1.itb.misses 62588 # DTB misses
|
|
system.cpu1.itb.accesses 447265251 # DTB accesses
|
|
system.cpu1.numPwrStateTransitions 12622 # Number of power state transitions
|
|
system.cpu1.pwrStateClkGateDist::samples 6311 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::mean 7445577920.705118 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::stdev 138960729730.016388 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::underflows 4567 72.37% 72.37% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1000-5e+10 1718 27.22% 99.59% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.67% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.05% 99.71% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.75% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.03% 99.78% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::max_value 6953792880276 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::total 6311 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateResidencyTicks::ON 267180606430 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46989042257570 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.numCycles 94512452040 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 6311 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 446945594 # Number of instructions committed
|
|
system.cpu1.committedOps 534043093 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 497796457 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 375258 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 29044812 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 64056743 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 497796457 # number of integer instructions
|
|
system.cpu1.num_fp_insts 375258 # number of float instructions
|
|
system.cpu1.num_int_register_reads 659899184 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 389220604 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 611056 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 302696 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 95980638 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 95700174 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 176965712 # number of memory refs
|
|
system.cpu1.num_load_insts 93216701 # Number of load instructions
|
|
system.cpu1.num_store_insts 83749011 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 93978090791.450775 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 534361248.549225 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.005654 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.994346 # Percentage of idle cycles
|
|
system.cpu1.Branches 98364194 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 356129610 66.65% 66.65% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 1162336 0.22% 66.86% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 62196 0.01% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMultAcc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMisc 36452 0.01% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.88% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 93166406 17.44% 84.32% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 83460500 15.62% 99.94% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMemRead 50295 0.01% 99.95% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMemWrite 288511 0.05% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 534356306 # Class of executed instruction
|
|
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.tags.replacements 6135169 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 439.724728 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 170720636 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 6135681 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 27.824236 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 8470256211500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.724728 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858837 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.858837 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 360116437 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 360116437 # Number of data accesses
|
|
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 86463703 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 86463703 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 79472088 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 79472088 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 192310 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 192310 # number of SoftPFReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 67346 # number of WriteLineReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::total 67346 # number of WriteLineReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2116228 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 2116228 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2109994 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 2109994 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 166003137 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 166003137 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 166195447 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 166195447 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 3476659 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 3476659 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1488439 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1488439 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 809340 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 809340 # number of SoftPFReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 440862 # number of WriteLineReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::total 440862 # number of WriteLineReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151875 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 151875 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156847 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 156847 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 5405960 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 5405960 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 6215300 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 6215300 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 89940362 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 89940362 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 80960527 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 80960527 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 1001650 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 1001650 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 508208 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::total 508208 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2268103 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 2268103 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2266841 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 2266841 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 171409097 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 171409097 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 172410747 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 172410747 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038655 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.038655 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018385 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.018385 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808007 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808007 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.867483 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.867483 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066961 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066961 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069192 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031538 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.031538 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036049 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.036049 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.writebacks::writebacks 6135169 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 6135169 # number of writebacks
|
|
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.tags.replacements 4821762 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 496.439302 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 442436403 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 4822274 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 91.748499 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 8470184249000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439302 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 899339628 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 899339628 # Number of data accesses
|
|
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 442436403 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 442436403 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 442436403 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 442436403 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 442436403 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 442436403 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 4822274 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 4822274 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 4822274 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 4822274 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 4822274 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 4822274 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 447258677 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 447258677 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 447258677 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 447258677 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 447258677 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 447258677 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010782 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.010782 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010782 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.010782 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010782 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.010782 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.writebacks::writebacks 4821762 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 4821762 # number of writebacks
|
|
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.l2cache.tags.replacements 2257136 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 13044.860493 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 8980176 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 2273016 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 3.950776 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 13005.388479 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.571640 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.900374 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.793786 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001378 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001032 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.796195 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15820 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 29 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 398 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7364 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.965576 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 376404615 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 376404615 # Number of data accesses
|
|
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 350077 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155851 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 505928 # number of ReadReq hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::writebacks 4161473 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::total 4161473 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackClean_hits::writebacks 6795092 # number of WritebackClean hits
|
|
system.cpu1.l2cache.WritebackClean_hits::total 6795092 # number of WritebackClean hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621244 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 621244 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4351439 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::total 4351439 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3193387 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::total 3193387 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167103 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::total 167103 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 350077 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155851 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 4351439 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 3814631 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 8671998 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 350077 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155851 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 4351439 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 3814631 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 8671998 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22799 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11519 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 34318 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141879 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 141879 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156847 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 156847 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 725316 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 725316 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470835 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::total 470835 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1244487 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::total 1244487 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 273759 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::total 273759 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22799 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11519 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 470835 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 1969803 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 2474956 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22799 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11519 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 470835 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 1969803 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 2474956 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 372876 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167370 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 540246 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4161473 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::total 4161473 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6795092 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::total 6795092 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 141879 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 141879 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156847 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 156847 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1346560 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 1346560 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4822274 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::total 4822274 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4437874 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::total 4437874 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 440862 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::total 440862 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 372876 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167370 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 4822274 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 5784434 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 11146954 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 372876 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167370 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 4822274 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 5784434 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 11146954 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068824 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.063523 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538644 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538644 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097638 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097638 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.280424 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.280424 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620963 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620963 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068824 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097638 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340535 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.222030 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068824 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097638 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340535 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.222030 # miss rate for overall accesses
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.writebacks::writebacks 1247214 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 1247214 # number of writebacks
|
|
system.cpu1.toL2Bus.snoop_filter.tot_requests 22589206 # Total number of requests made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11541877 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.tot_snoops 281509 # Total number of snoops made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 281509 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 627108 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 9887256 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 6357 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 6357 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4161473 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackClean 6795458 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 141879 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156847 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 298726 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 1346560 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 1346560 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4822274 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4437874 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateReq 440862 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateResp 440862 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14466570 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19208649 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374184 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 867050 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 34916453 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617218824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 762892902 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1496736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3468200 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 1385076662 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 4471176 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoopTraffic 86426880 # Total snoop traffic (bytes)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 27252775 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 0.020850 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.142882 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 26684555 97.92% 97.92% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 568220 2.08% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 27252775 # Request fanout histogram
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 40208 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40208 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136550 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136550 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47302 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122236 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353516 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47322 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155343 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7496245 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 115580 # number of replacements
|
|
system.iocache.tags.tagsinuse 11.294790 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115596 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 9107754177509 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.848737 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 7.446053 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.240546 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.465378 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.705924 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1040757 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1040757 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 115600 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 115640 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 115600 # number of overall misses
|
|
system.iocache.overall_misses::total 115640 # number of overall misses
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 115600 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 115640 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 115600 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 115640 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 106693 # number of writebacks
|
|
system.iocache.writebacks::total 106693 # number of writebacks
|
|
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.tags.replacements 2000796 # number of replacements
|
|
system.l2c.tags.tagsinuse 65236.747854 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 5872089 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 2062236 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 2.847438 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 458916500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 10773.265369 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.425728 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 60.472796 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 3088.117960 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 16913.790714 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 343.005231 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 383.707168 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 2970.710524 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 30646.252365 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.164387 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000876 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000923 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.047121 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.258084 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005234 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.005855 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.045329 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.467625 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.995434 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 61204 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3527 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 4478 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 52898 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.933899 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 73224508 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 73224508 # Number of data accesses
|
|
system.l2c.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.WritebackDirty_hits::writebacks 2843148 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 2843148 # number of WritebackDirty hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 57335 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 51488 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 108823 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 8370 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 7752 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 16122 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 205747 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 172848 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 378595 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13551 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5506 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.inst 436242 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 735903 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12336 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4370 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.inst 421904 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 692405 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 2322217 # number of ReadSharedReq hits
|
|
system.l2c.InvalidateReq_hits::cpu0.data 112000 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::cpu1.data 99469 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::total 211469 # number of InvalidateReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 13551 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 5506 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 436242 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 941650 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 12336 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 4370 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 421904 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 865253 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2700812 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 13551 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 5506 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 436242 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 941650 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 12336 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 4370 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 421904 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 865253 # number of overall hits
|
|
system.l2c.overall_hits::total 2700812 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 20153 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 22374 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 42527 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 465 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1417 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 404904 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 443379 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 848283 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2501 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1981 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.inst 60987 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 188974 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3841 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3819 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.inst 48931 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 203657 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 514691 # number of ReadSharedReq misses
|
|
system.l2c.InvalidateReq_misses::cpu0.data 441546 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::cpu1.data 132806 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::total 574352 # number of InvalidateReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 2501 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1981 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 60987 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 593878 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 3841 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 3819 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 48931 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 647036 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 1362974 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 2501 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1981 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 60987 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 593878 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 3841 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 3819 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 48931 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 647036 # number of overall misses
|
|
system.l2c.overall_misses::total 1362974 # number of overall misses
|
|
system.l2c.WritebackDirty_accesses::writebacks 2843148 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 2843148 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 77488 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 73862 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 151350 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 8835 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 8704 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 17539 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 610651 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 616227 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 1226878 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16052 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7487 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 924877 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16177 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8189 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.inst 470835 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 896062 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 2836908 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu0.data 553546 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu1.data 232275 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::total 785821 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 16052 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 7487 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1535528 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 16177 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 8189 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 470835 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 1512289 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 4063786 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 16052 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 7487 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1535528 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 16177 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 8189 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 470835 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 1512289 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 4063786 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260079 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.302916 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.280984 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.052632 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.109375 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.080791 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.663069 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.719506 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.691416 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.264592 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.122654 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.204323 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.466357 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.103924 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.227280 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.181427 # miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.797668 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.571762 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::total 0.730894 # miss rate for InvalidateReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.264592 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.122654 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.386758 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.466357 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.103924 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.427852 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.335395 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.264592 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.122654 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.386758 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.466357 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.103924 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.427852 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.335395 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 1557006 # number of writebacks
|
|
system.l2c.writebacks::total 1557006 # number of writebacks
|
|
system.membus.snoop_filter.tot_requests 4511574 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 2519656 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 3180 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 43614 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 567214 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 38678 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 38678 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 1663699 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 266504 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 223308 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 295373 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 46773 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 849453 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 845457 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 523600 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 689636 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 681080 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122236 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27410 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6276469 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 6426207 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 346860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 6773067 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155343 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54820 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 186738012 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 186948379 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7398528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 194346907 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 4593865 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.007098 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.083952 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 4561256 99.29% 99.29% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 32609 0.71% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 4593865 # Request fanout histogram
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.snoop_filter.tot_requests 11315905 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 5737208 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1831359 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 298423 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 272858 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 25565 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.trans_dist::ReadReq 43616 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 3567484 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 38678 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 38678 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 2843148 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 2033600 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 329302 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 311495 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 640797 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 1403084 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 1403084 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 3523868 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 871405 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateResp 871405 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9542040 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8377604 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 17919644 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260882877 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 236654062 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 497536939 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 2048171 # Total snoops (count)
|
|
system.toL2Bus.snoopTraffic 99695936 # Total snoop traffic (bytes)
|
|
system.toL2Bus.snoop_fanout::samples 13430913 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.303362 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.463832 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 9382052 69.85% 69.85% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 4023296 29.96% 99.81% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 25565 0.19% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 13430913 # Request fanout histogram
|
|
|
|
---------- End Simulation Statistics ----------
|