sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
Andreas Hansson f2e2410a50 stats: Get all stats updated to reflect current behaviour 
Line everything up again.
2017-02-19 05:30:32 -05:00

3410 lines
410 KiB
Plaintext
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 47.310816 # Number of seconds simulated
sim_ticks 47310816168000 # Number of ticks simulated
final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 279196 # Simulator instruction rate (inst/s)
host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
host_mem_usage 770320 # Number of bytes of host memory used
host_seconds 2980.95 # Real time elapsed on the host
sim_insts 832269934 # Number of instructions simulated
sim_ops 991180133 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1084146 # Number of read requests accepted
system.physmem.writeReqs 1315173 # Number of write requests accepted
system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 69238 # Per bank write bursts
system.physmem.perBankRdBursts::1 72128 # Per bank write bursts
system.physmem.perBankRdBursts::2 62859 # Per bank write bursts
system.physmem.perBankRdBursts::3 64909 # Per bank write bursts
system.physmem.perBankRdBursts::4 64833 # Per bank write bursts
system.physmem.perBankRdBursts::5 74280 # Per bank write bursts
system.physmem.perBankRdBursts::6 68552 # Per bank write bursts
system.physmem.perBankRdBursts::7 74109 # Per bank write bursts
system.physmem.perBankRdBursts::8 62269 # Per bank write bursts
system.physmem.perBankRdBursts::9 70311 # Per bank write bursts
system.physmem.perBankRdBursts::10 59842 # Per bank write bursts
system.physmem.perBankRdBursts::11 70232 # Per bank write bursts
system.physmem.perBankRdBursts::12 64744 # Per bank write bursts
system.physmem.perBankRdBursts::13 72876 # Per bank write bursts
system.physmem.perBankRdBursts::14 66012 # Per bank write bursts
system.physmem.perBankRdBursts::15 66520 # Per bank write bursts
system.physmem.perBankWrBursts::0 83559 # Per bank write bursts
system.physmem.perBankWrBursts::1 83793 # Per bank write bursts
system.physmem.perBankWrBursts::2 79464 # Per bank write bursts
system.physmem.perBankWrBursts::3 82775 # Per bank write bursts
system.physmem.perBankWrBursts::4 80648 # Per bank write bursts
system.physmem.perBankWrBursts::5 87124 # Per bank write bursts
system.physmem.perBankWrBursts::6 80406 # Per bank write bursts
system.physmem.perBankWrBursts::7 83854 # Per bank write bursts
system.physmem.perBankWrBursts::8 77300 # Per bank write bursts
system.physmem.perBankWrBursts::9 82321 # Per bank write bursts
system.physmem.perBankWrBursts::10 78447 # Per bank write bursts
system.physmem.perBankWrBursts::11 84798 # Per bank write bursts
system.physmem.perBankWrBursts::12 79286 # Per bank write bursts
system.physmem.perBankWrBursts::13 85569 # Per bank write bursts
system.physmem.perBankWrBursts::14 81705 # Per bank write bursts
system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
system.physmem.totGap 47310814104000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
system.physmem.totQLat 57570179828 # Total ticks spent queuing
system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
system.physmem.readRowHits 798943 # Number of row buffer hits during reads
system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
system.physmem.avgGap 19718434.32 # Average gap between requests
system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 91107490 # DTB read hits
system.cpu0.dtb.read_misses 238663 # DTB read misses
system.cpu0.dtb.write_hits 81148084 # DTB write hits
system.cpu0.dtb.write_misses 53270 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 172255574 # DTB hits
system.cpu0.dtb.misses 291933 # DTB misses
system.cpu0.dtb.accesses 172547507 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 65131 # Table walker walks requested
system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 201165320 # ITB inst hits
system.cpu0.itb.inst_misses 65131 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
system.cpu0.itb.hits 201165320 # DTB hits
system.cpu0.itb.misses 65131 # DTB misses
system.cpu0.itb.accesses 201230451 # DTB accesses
system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 923231946 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 433947137 # Number of instructions committed
system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.127522 # CPI: cycles per instruction
system.cpu0.ipc 0.470030 # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::total 516803462 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6005277 # number of replacements
system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits
system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses
system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks
system.cpu0.dcache.writebacks::total 6005280 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 9998472 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits
system.cpu0.icache.overall_hits::total 190986664 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses
system.cpu0.icache.overall_misses::total 9998995 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks
system.cpu0.icache.writebacks::total 9998472 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2932551 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9224160 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2947596 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 13847889 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539317 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits
system.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses
system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257791 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 257791 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202293 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 202293 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289245 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 289245 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 774834 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 774834 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1075153 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1075153 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597922 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 597922 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21966 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10468 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 774834 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1364398 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2171666 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21966 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10468 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 774834 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1364398 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2171666 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 715984000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 391759500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 1107743500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 860565000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 860565000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 334549500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 334549500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1814999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1814999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15808379497 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 15808379497 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 28621690500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 28621690500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40818686990 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40818686990 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 715984000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 391759500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 28621690500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 56627066487 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 86356500487 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 715984000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 391759500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 28621690500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 56627066487 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 86356500487 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 561283 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175522 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 736805 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3976191 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 3976191 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 12024319 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 12024319 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257791 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 257791 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202293 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 202293 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1261007 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1261007 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9998994 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 9998994 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4022749 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4022749 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 807604 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 807604 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 561283 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175522 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 9998994 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5283756 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 16019555 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 561283 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175522 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 9998994 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5283756 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 16019555 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059639 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.044020 # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229376 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229376 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.077491 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.077491 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267268 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267268 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.740365 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.740365 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059639 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.077491 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258225 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.135563 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059639 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.077491 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258225 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.135563 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37424.484142 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34153.773818 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3338.227479 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3338.227479 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1653.786834 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1653.786834 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 453749.750000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 453749.750000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54653.942149 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54653.942149 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36939.125671 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36939.125671 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37965.468161 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37965.468161 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.173936 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.173936 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39765.093015 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39765.093015 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches 48917 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 1795601 # number of writebacks
system.cpu0.l2cache.writebacks::total 1795601 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 90 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10129 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 10129 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 992 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 992 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 90 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11121 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 90 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11121 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 11245 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21943 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10378 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 32321 # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 836449 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257791 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257791 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202293 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202293 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279116 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 279116 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 774823 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 2160421 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 85144665 # DTB read hits
system.cpu1.dtb.read_misses 232605 # DTB read misses
system.cpu1.dtb.write_hits 73861979 # DTB write hits
system.cpu1.dtb.write_misses 45370 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 159006644 # DTB hits
system.cpu1.dtb.misses 277975 # DTB misses
system.cpu1.dtb.accesses 159284619 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 63204 # Table walker walks requested
system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 184175570 # ITB inst hits
system.cpu1.itb.inst_misses 63204 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
system.cpu1.itb.hits 184175570 # DTB hits
system.cpu1.itb.misses 63204 # DTB misses
system.cpu1.itb.accesses 184238774 # DTB accesses
system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 798693745 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 398322797 # Number of instructions committed
system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.005142 # CPI: cycles per instruction
system.cpu1.ipc 0.498718 # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::total 474376671 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5132038 # number of replacements
system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits
system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses
system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks
system.cpu1.dcache.writebacks::total 5132050 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 8722673 # number of replacements
system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits
system.cpu1.icache.overall_hits::total 175283400 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses
system.cpu1.icache.overall_misses::total 8723185 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks
system.cpu1.icache.writebacks::total 8722673 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2217652 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000925 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 860878 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8051210 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 8051210 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2757056 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2757056 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173091 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 173091 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532002 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159372 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 8051210 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3617934 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 12360518 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532002 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159372 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 8051210 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3617934 # number of overall hits
system.cpu1.l2cache.overall_hits::total 12360518 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21589 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10425 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 32014 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206575 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 206575 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199341 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 199341 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 222346 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 222346 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 671975 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 671975 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 945788 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 945788 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266132 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10425 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1168134 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1872123 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21589 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10425 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1168134 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1872123 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 733662000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 446226000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1179888000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 870385500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 311325000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 11310487497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 23715219500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36332241992 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36332241992 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 733662000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 446226000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 72537836989 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 72537836989 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 553591 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 723388 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3201676 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3201676 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 10651334 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1083224 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1083224 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8723185 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 8723185 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3702844 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3702844 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439223 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 439223 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 553591 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169797 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 8723185 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4786068 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 14232641 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 553591 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169797 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 8723185 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4786068 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 14232641 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061397 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.044256 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.205263 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.205263 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077033 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077033 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255422 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255422 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.605915 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.605915 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061397 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077033 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244070 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.131537 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061397 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077033 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244070 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.131537 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42803.453237 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36855.375773 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4213.411594 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4213.411594 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1561.771036 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1561.771036 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 643333.333333 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 643333.333333 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50868.859782 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50868.859782 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35291.818148 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35291.818148 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38414.784277 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38414.784277 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 38746.298715 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks
system.cpu1.l2cache.writebacks::total 1164875 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115597 # number of replacements
system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040910 # Number of tag accesses
system.iocache.tags.data_accesses 1040910 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses
system.iocache.demand_misses::total 115657 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115617 # number of overall misses
system.iocache.overall_misses::total 115657 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles
system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106693 # number of writebacks
system.iocache.writebacks::total 106693 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1609900 # number of replacements
system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use
system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 82772579 # Number of tag accesses
system.l2c.tags.data_accesses 82772579 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2960473 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2960473 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 214775 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 151269 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 366044 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 56896 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 55474 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 112370 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 67148 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 118780 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 14203 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 6226 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 695308 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 685955 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 328258 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12341 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4684 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 616265 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 560248 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 290505 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 3213993 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 136732 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 122714 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 259446 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 14203 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6226 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 695308 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 753103 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 328258 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12341 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4684 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 616265 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 611880 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 290505 # number of demand (read+write) hits
system.l2c.demand_hits::total 3332773 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 14203 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6226 # number of overall hits
system.l2c.overall_hits::cpu0.inst 695308 # number of overall hits
system.l2c.overall_hits::cpu0.data 753103 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 328258 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12341 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4684 # number of overall hits
system.l2c.overall_hits::cpu1.inst 616265 # number of overall hits
system.l2c.overall_hits::cpu1.data 611880 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 290505 # number of overall hits
system.l2c.overall_hits::total 3332773 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 20148 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 22532 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 42680 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 632 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1574 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 82382 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 53449 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 135831 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1618 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 79514 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 147489 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2403 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 55709 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 138924 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 938667 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 422083 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 110180 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 532263 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2080 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1618 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 79514 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 229871 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2595 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2403 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 55709 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 192373 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) misses
system.l2c.demand_misses::total 1074498 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2080 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1618 # number of overall misses
system.l2c.overall_misses::cpu0.inst 79514 # number of overall misses
system.l2c.overall_misses::cpu0.data 229871 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 271925 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2595 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2403 # number of overall misses
system.l2c.overall_misses::cpu1.inst 55709 # number of overall misses
system.l2c.overall_misses::cpu1.data 192373 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 236410 # number of overall misses
system.l2c.overall_misses::total 1074498 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 146038500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 131790500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 277829000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10352000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8549500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 18901500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8710976500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5673543000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 14384519500 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 219387000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 170599500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8581562500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 16399499000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257094000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 237286000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6184697999 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15199077000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 118434367320 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 219387000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 170599500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 8581562500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 25110475500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 257094000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 237286000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6184697999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 20872620000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 132818886820 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 219387000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 170599500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 8581562500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 25110475500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 257094000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 237286000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 6184697999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 20872620000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of overall miss cycles
system.l2c.overall_miss_latency::total 132818886820 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 2960473 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2960473 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 234923 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 173801 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 408724 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 57528 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 56416 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 113944 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 149530 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 105081 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 254611 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16283 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7844 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 774822 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 833444 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 600183 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14936 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7087 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 671974 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 699172 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 526915 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 4152660 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 558815 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 232894 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 791709 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 16283 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 7844 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 774822 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 982974 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 600183 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 14936 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7087 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 671974 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 804253 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526915 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4407271 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 16283 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 7844 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 774822 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 982974 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 600183 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 14936 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7087 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 671974 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 804253 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526915 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4407271 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.085764 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129643 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.104423 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010986 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016697 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.013814 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.550940 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.508646 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.533484 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.206272 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102622 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.176963 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339072 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.082904 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.198698 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.226040 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.755318 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.473091 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.672296 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.206272 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.102622 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.233853 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.339072 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.082904 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.239195 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.243801 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.206272 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.102622 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.233853 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.339072 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.082904 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.239195 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.243801 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7248.287671 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5849.036925 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 6509.582943 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16379.746835 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9075.902335 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 12008.576874 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 105738.832512 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106148.721211 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 105900.122211 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105438.504326 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107925.176698 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111191.336303 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 98745.734499 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111017.932453 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 109405.696640 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 126172.931743 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123610.175933 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123610.175933 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 1362 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 104.769231 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 1205906 # number of writebacks
system.l2c.writebacks::total 1205906 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 38 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 160 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 380 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 160 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 160 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 380 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 74973 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 74973 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 20148 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 22532 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 42680 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 632 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1574 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 82382 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 53449 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 135831 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1618 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 79343 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147451 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2403 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55549 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 138913 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 938287 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 422083 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 110180 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 532263 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2080 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1618 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 79343 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 229833 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2595 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2403 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 55549 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 192362 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 1074118 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2080 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1618 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 79343 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 229833 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2595 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2403 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 55549 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 192362 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 1074118 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5328 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 42476 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 37999 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10594 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 80475 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 406966500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 461692998 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 868659498 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15287999 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22938500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 38226499 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7887118579 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5139033541 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 13026152120 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154419500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7774295554 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14921316255 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213255501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5614526528 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13808714201 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 109017709147 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8734501501 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2122534500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 10857036001 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154419500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 7774295554 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 22808434834 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213255501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 5614526528 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 18947747742 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 122043861267 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154419500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 7774295554 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 22808434834 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213255501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 5614526528 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 18947747742 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 122043861267 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 303607000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5434541500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6865000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 495854501 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6240868001 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 303607000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5434541500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6865000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495854501 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6240868001 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129643 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.104423 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010986 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016697 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013814 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550940 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508646 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.533484 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.176918 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 42476 # Transaction distribution
system.membus.trans_dist::ReadResp 989688 # Transaction distribution
system.membus.trans_dist::WriteReq 37999 # Transaction distribution
system.membus.trans_dist::WriteResp 37999 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution
system.membus.trans_dist::CleanEvict 291937 # Transaction distribution
system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution
system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 150791 # Transaction distribution
system.membus.trans_dist::ReadExResp 135122 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution
system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution
system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 586564 # Total snoops (count)
system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2402773 # Request fanout histogram
system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3035429 # Total snoops (count)
system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink