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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
Andreas Hansson f2e2410a50 stats: Get all stats updated to reflect current behaviour 
Line everything up again.
2017-02-19 05:30:32 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 47.341923 # Number of seconds simulated
sim_ticks 47341923254000 # Number of ticks simulated
final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 198941 # Simulator instruction rate (inst/s)
host_op_rate 237233 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10723675807 # Simulator tick rate (ticks/s)
host_mem_usage 786956 # Number of bytes of host memory used
host_seconds 4414.71 # Real time elapsed on the host
sim_insts 878265186 # Number of instructions simulated
sim_ops 1047316960 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory
system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1277902 # Number of read requests accepted
system.physmem.writeReqs 1529475 # Number of write requests accepted
system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue
system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 74308 # Per bank write bursts
system.physmem.perBankRdBursts::1 87985 # Per bank write bursts
system.physmem.perBankRdBursts::2 79775 # Per bank write bursts
system.physmem.perBankRdBursts::3 80704 # Per bank write bursts
system.physmem.perBankRdBursts::4 79279 # Per bank write bursts
system.physmem.perBankRdBursts::5 87661 # Per bank write bursts
system.physmem.perBankRdBursts::6 78349 # Per bank write bursts
system.physmem.perBankRdBursts::7 78833 # Per bank write bursts
system.physmem.perBankRdBursts::8 69442 # Per bank write bursts
system.physmem.perBankRdBursts::9 78370 # Per bank write bursts
system.physmem.perBankRdBursts::10 69793 # Per bank write bursts
system.physmem.perBankRdBursts::11 81996 # Per bank write bursts
system.physmem.perBankRdBursts::12 80451 # Per bank write bursts
system.physmem.perBankRdBursts::13 82396 # Per bank write bursts
system.physmem.perBankRdBursts::14 80116 # Per bank write bursts
system.physmem.perBankRdBursts::15 88030 # Per bank write bursts
system.physmem.perBankWrBursts::0 92185 # Per bank write bursts
system.physmem.perBankWrBursts::1 101129 # Per bank write bursts
system.physmem.perBankWrBursts::2 94103 # Per bank write bursts
system.physmem.perBankWrBursts::3 97328 # Per bank write bursts
system.physmem.perBankWrBursts::4 94264 # Per bank write bursts
system.physmem.perBankWrBursts::5 99023 # Per bank write bursts
system.physmem.perBankWrBursts::6 94391 # Per bank write bursts
system.physmem.perBankWrBursts::7 95568 # Per bank write bursts
system.physmem.perBankWrBursts::8 90026 # Per bank write bursts
system.physmem.perBankWrBursts::9 95851 # Per bank write bursts
system.physmem.perBankWrBursts::10 88927 # Per bank write bursts
system.physmem.perBankWrBursts::11 96294 # Per bank write bursts
system.physmem.perBankWrBursts::12 94934 # Per bank write bursts
system.physmem.perBankWrBursts::13 97047 # Per bank write bursts
system.physmem.perBankWrBursts::14 95210 # Per bank write bursts
system.physmem.perBankWrBursts::15 100911 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry
system.physmem.totGap 47341921675500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 2133 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1275744 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1526901 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads
system.physmem.totQLat 79629370316 # Total ticks spent queuing
system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers
system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing
system.physmem.readRowHits 958718 # Number of row buffer hits during reads
system.physmem.writeRowHits 675564 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes
system.physmem.avgGap 16863400.13 # Average gap between requests
system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ)
system.physmem_0.averagePower 242.399417 # Core power per rank (mW)
system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states
system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states
system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states
system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ)
system.physmem_1.averagePower 242.420579 # Core power per rank (mW)
system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states
system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states
system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 135771616 # Number of BP lookups
system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 656993 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 107772870 # DTB read hits
system.cpu0.dtb.read_misses 484010 # DTB read misses
system.cpu0.dtb.write_hits 87417439 # DTB write hits
system.cpu0.dtb.write_misses 172983 # DTB write misses
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 108256880 # DTB read accesses
system.cpu0.dtb.write_accesses 87590422 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 195190309 # DTB hits
system.cpu0.dtb.misses 656993 # DTB misses
system.cpu0.dtb.accesses 195847302 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 88518 # Table walker walks requested
system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 209275517 # ITB inst hits
system.cpu0.itb.inst_misses 88518 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses
system.cpu0.itb.hits 209275517 # DTB hits
system.cpu0.itb.misses 88518 # DTB misses
system.cpu0.itb.accesses 209364035 # DTB accesses
system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 671656145 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued
system.cpu0.iq.rate 0.884706 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 135817 # number of nop insts executed
system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed
system.cpu0.iew.exec_branches 107644173 # Number of branches executed
system.cpu0.iew.exec_stores 87417057 # Number of stores executed
system.cpu0.iew.exec_rate 0.872488 # Inst execution rate
system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 283557258 # num instructions producing a value
system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 461890383 # Number of instructions committed
system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 179586814 # Number of memory references committed
system.cpu0.commit.loads 94510447 # Number of loads committed
system.cpu0.commit.membars 4189650 # Number of memory barriers committed
system.cpu0.commit.branches 102007560 # Number of branches committed
system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions.
system.cpu0.commit.function_calls 15004572 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction
system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads
system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes
system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 461890383 # Number of Instructions Simulated
system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads
system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes
system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads
system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes
system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads
system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads
system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6620968 # number of replacements
system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits
system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses
system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks
system.cpu0.dcache.writebacks::total 6621095 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 6024041 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits
system.cpu0.icache.overall_hits::total 202652654 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses
system.cpu0.icache.overall_misses::total 6379961 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks
system.cpu0.icache.writebacks::total 6024041 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 64522792922 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64522792922 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 64522792922 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 201228498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028822 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2885626 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 1063752 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5420251 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3451457 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175529 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 4515209 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 10789447 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits
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system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14042647500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19039385000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19039385000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39727406492 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39727406492 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22010835496 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22010835496 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519315500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19039385000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53770053992 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 74092172492 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519315500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19039385000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53770053992 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 140358570236 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 185530000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2769951000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 2955481000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 185530000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 124325317 # Number of BP lookups
system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 580775 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 97816184 # DTB read hits
system.cpu1.dtb.read_misses 397931 # DTB read misses
system.cpu1.dtb.write_hits 81264416 # DTB write hits
system.cpu1.dtb.write_misses 182844 # DTB write misses
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 98214115 # DTB read accesses
system.cpu1.dtb.write_accesses 81447260 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 179080600 # DTB hits
system.cpu1.dtb.misses 580775 # DTB misses
system.cpu1.dtb.accesses 179661375 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 87135 # Table walker walks requested
system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 190777093 # ITB inst hits
system.cpu1.itb.inst_misses 87135 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses
system.cpu1.itb.hits 190777093 # DTB hits
system.cpu1.itb.misses 87135 # DTB misses
system.cpu1.itb.accesses 190864228 # DTB accesses
system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 605218102 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued
system.cpu1.iq.rate 0.892811 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 138202 # number of nop insts executed
system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed
system.cpu1.iew.exec_branches 97312103 # Number of branches executed
system.cpu1.iew.exec_stores 81264721 # Number of stores executed
system.cpu1.iew.exec_rate 0.879706 # Inst execution rate
system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 254758095 # num instructions producing a value
system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 416374803 # Number of instructions committed
system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 164651061 # Number of memory references committed
system.cpu1.commit.loads 85667366 # Number of loads committed
system.cpu1.commit.membars 3698541 # Number of memory barriers committed
system.cpu1.commit.branches 91988554 # Number of branches committed
system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13152854 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction
system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads
system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes
system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 416374803 # Number of Instructions Simulated
system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads
system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes
system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads
system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes
system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads
system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads
system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5530000 # number of replacements
system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits
system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses
system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks
system.cpu1.dcache.writebacks::total 5530029 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 6156366 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits
system.cpu1.icache.overall_hits::total 184011394 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses
system.cpu1.icache.overall_misses::total 6513585 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks
system.cpu1.icache.writebacks::total 6156366 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6157012 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 6157012 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2237289 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021973 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.935303 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 407515579 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 407515579 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 593172 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 194279 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 787451 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3518569 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3518569 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 8164233 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 8164233 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 105 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 105 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 954506 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 954506 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5573390 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 5573390 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2940198 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2940198 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 209295 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 593172 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 194279 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 5573390 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3894704 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 10255545 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 593172 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 194279 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 5573390 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3894704 # number of overall hits
system.cpu1.l2cache.overall_hits::total 10255545 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 23430 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10710 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 34140 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 228701 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 228701 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195469 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 195469 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254871 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 254871 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 583583 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 583583 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1000824 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1000824 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 253175 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 253175 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 23430 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10710 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 583583 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1255695 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1873418 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 23430 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10710 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 583583 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1255695 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1873418 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 794453000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 411582000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 1206035000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 885247000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 885247000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 309725000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 309725000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2651498 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2651498 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13048454496 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 13048454496 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21566356000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21566356000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38197437985 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38197437985 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 1037000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 1037000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 794453000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 411582000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 51245892481 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 74018283481 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 794453000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 411582000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21566356000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 51245892481 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 74018283481 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 616602 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 204989 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 821591 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3518569 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3518569 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 8164233 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 8164233 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228806 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 195470 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1209377 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1209377 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6156973 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 6156973 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3941022 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3941022 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 462470 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 462470 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 616602 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 204989 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 6156973 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5150399 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 12128963 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 616602 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 204989 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 6156973 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5150399 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 12128963 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052247 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.041554 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999541 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999541 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210746 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210746 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094784 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094784 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253950 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253950 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.547441 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.547441 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052247 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094784 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243805 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.154458 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052247 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094784 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243805 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.154458 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38429.691877 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35326.157001 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3870.761387 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3870.761387 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1584.522354 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1584.522354 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 294610.888889 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 294610.888889 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51196.309098 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51196.309098 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36955.079226 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36955.079226 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38165.989210 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38165.989210 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 4.095981 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 4.095981 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 39509.753553 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 39509.753553 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.500000 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 45092 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1265703 # number of writebacks
system.cpu1.l2cache.writebacks::total 1265703 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 89 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 277 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 14520 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40285 # Transaction distribution
system.iobus.trans_dist::ReadResp 40285 # Transaction distribution
system.iobus.trans_dist::WriteReq 136579 # Transaction distribution
system.iobus.trans_dist::WriteResp 136579 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115633 # number of replacements
system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040946 # Number of tag accesses
system.iocache.tags.data_accesses 1040946 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses
system.iocache.demand_misses::total 115661 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115621 # number of overall misses
system.iocache.overall_misses::total 115661 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106710 # number of writebacks
system.iocache.writebacks::total 106710 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1858608 # number of replacements
system.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use
system.l2c.tags.total_refs 7355255 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.056986 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 84121444 # Number of tag accesses
system.l2c.tags.data_accesses 84121444 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 59150 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113470 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13417 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5017 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 539007 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 668528 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 293105 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15148 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 6130 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 525725 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 626529 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298432 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2991038 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 122623 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits
system.l2c.demand_hits::total 3104508 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 13417 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5017 # number of overall hits
system.l2c.overall_hits::cpu0.inst 539007 # number of overall hits
system.l2c.overall_hits::cpu0.data 722848 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 293105 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 15148 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6130 # number of overall hits
system.l2c.overall_hits::cpu1.inst 525725 # number of overall hits
system.l2c.overall_hits::cpu1.data 685679 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 298432 # number of overall hits
system.l2c.overall_hits::total 3104508 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 21614 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 22773 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 44387 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1033 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1052 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2085 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 96389 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 53149 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 149538 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3652 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 65121 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 199292 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 394602 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1730 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 57847 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 128371 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 1121106 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 461443 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 96191 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 557634 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 3784 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3652 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 65121 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 295681 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 394602 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2497 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1730 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 57847 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 181520 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) misses
system.l2c.demand_misses::total 1270644 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 3784 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3652 # number of overall misses
system.l2c.overall_misses::cpu0.inst 65121 # number of overall misses
system.l2c.overall_misses::cpu0.data 295681 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 394602 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2497 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1730 # number of overall misses
system.l2c.overall_misses::cpu1.inst 57847 # number of overall misses
system.l2c.overall_misses::cpu1.data 181520 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 264210 # number of overall misses
system.l2c.overall_misses::total 1270644 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 151083000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 144162500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 295245500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9029500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10650000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 19679500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 10395447993 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5744671997 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 16140119990 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 381693500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 359292500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7105700999 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 21857572496 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 266793000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 185648500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6445588500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15192688491 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 153222588727 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 381693500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 359292500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 7105700999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 32253020489 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 266793000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 185648500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6445588500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 20937360488 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 169362708717 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 381693500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 359292500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 7105700999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 32253020489 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 266793000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 185648500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 6445588500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 20937360488 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of overall miss cycles
system.l2c.overall_miss_latency::total 169362708717 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 3161961 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 3161961 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 240087 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 201000 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 441087 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 61449 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 51213 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 112662 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150709 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 112299 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 263008 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 17201 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8669 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 604128 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 867820 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 687707 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 17645 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7860 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 583572 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 754900 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 562642 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 4112144 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 584066 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 217282 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 801348 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 17201 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 8669 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 604128 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1018529 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 687707 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 17645 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7860 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 583572 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 867199 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 562642 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4375152 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 17201 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 8669 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 604128 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1018529 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 687707 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 17645 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7860 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 583572 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 867199 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 562642 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4375152 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090026 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.113299 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.100631 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016811 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020542 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.018507 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.639570 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.473281 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.568568 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.421271 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107793 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.229647 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.220102 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.099126 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.170050 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.272633 # miss rate for ReadSharedReq accesses
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system.l2c.overall_avg_miss_latency::total 133288.874553 # average overall miss latency
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40965 # Transaction distribution
system.membus.trans_dist::ReadResp 1170673 # Transaction distribution
system.membus.trans_dist::WriteReq 38689 # Transaction distribution
system.membus.trans_dist::WriteResp 38689 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution
system.membus.trans_dist::CleanEvict 301973 # Transaction distribution
system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 162891 # Transaction distribution
system.membus.trans_dist::ReadExResp 148894 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution
system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution
system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 585668 # Total snoops (count)
system.membus.snoopTraffic 182912 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2626196 # Request fanout histogram
system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram
system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2626196 # Request fanout histogram
system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3295138 # Total snoops (count)
system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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