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stats: Bump stats to match DRAM controller changes

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This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
This commit is contained in:
Andreas Hansson 2013-11-01 11:56:34 -04:00
parent 460cc77d6d
commit ccfdc533b9
51 changed files with 44598 additions and 42183 deletions
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3808
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
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tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
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tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
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tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.139916 # Number of seconds simulated sim_seconds 0.139926 # Number of seconds simulated
sim_ticks 139916242500 # Number of ticks simulated sim_ticks 139926186500 # Number of ticks simulated
final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 80792 # Simulator instruction rate (inst/s) host_inst_rate 122800 # Simulator instruction rate (inst/s)
host_op_rate 80792 # Simulator op (including micro ops) rate (op/s) host_op_rate 122800 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28354866 # Simulator tick rate (ticks/s) host_tick_rate 43101138 # Simulator tick rate (ticks/s)
host_mem_usage 231004 # Number of bytes of host memory used host_mem_usage 261428 # Number of bytes of host memory used
host_seconds 4934.47 # Real time elapsed on the host host_seconds 3246.46 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 214976 # Nu
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 7328 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 468992 # Total number of bytes read from memory system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 507 # Per bank write bursts
system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 643 # Per bank write bursts
system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 444 # Per bank write bursts
system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 597 # Per bank write bursts
system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 448 # Per bank write bursts
system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 451 # Per bank write bursts
system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 505 # Per bank write bursts
system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 513 # Per bank write bursts
system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 423 # Per bank write bursts
system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 395 # Per bank write bursts
system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 336 # Per bank write bursts
system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 304 # Per bank write bursts
system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 416 # Per bank write bursts
system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 534 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 441 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 371 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 139916169000 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 139926113000 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7328 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 7328 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@ -150,98 +152,97 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation system.physmem.totQLat 59880500 # Total ticks spent queuing
system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers
system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation system.physmem.totBankLat 101103750 # Total ticks spent accessing banks
system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst
system.physmem.totQLat 39772250 # Total cycles spent in queuing delays system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst
system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.totBusLat 36640000 # Total cycles spent in databus access system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst
system.physmem.totBankLat 98628750 # Total cycles spent in bank access system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgQLat 5427.44 # Average queueing delay per request system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgBankLat 13459.16 # Average bank access latency per request system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.avgMemAccLat 23886.60 # Average memory access latency system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.readRowHits 6626 # Number of row buffer hits during reads system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6130 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19093363.67 # Average gap between requests system.physmem.avgGap 19094720.66 # Average gap between requests
system.membus.throughput 3351948 # Throughput (bytes/s) system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 3351710 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadReq 4183 # Transaction distribution
system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
@ -252,39 +253,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 468992 # Total data (bytes) system.membus.data_through_bus 468992 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.branchPred.lookups 53489675 # Number of BP lookups system.cpu.branchPred.lookups 53489673 # Number of BP lookups
system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754653 # DTB read hits system.cpu.dtb.read_hits 94754637 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754674 # DTB read accesses system.cpu.dtb.read_accesses 94754658 # DTB read accesses
system.cpu.dtb.write_hits 73521120 # DTB write hits system.cpu.dtb.write_hits 73521124 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73521155 # DTB write accesses system.cpu.dtb.write_accesses 73521159 # DTB write accesses
system.cpu.dtb.data_hits 168275773 # DTB hits system.cpu.dtb.data_hits 168275761 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275829 # DTB accesses system.cpu.dtb.data_accesses 168275817 # DTB accesses
system.cpu.itb.fetch_hits 48611327 # ITB hits system.cpu.itb.fetch_hits 48611324 # ITB hits
system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_misses 44520 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 48655847 # ITB accesses system.cpu.itb.fetch_accesses 48655844 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -298,18 +299,18 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 279832486 # number of cpu cycles simulated system.cpu.numCycles 279852374 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.agen_unit.agens 168485322 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
@ -320,12 +321,12 @@ system.cpu.execution_unit.executions 205475782 # Nu
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed.
system.cpu.activity 95.166455 # Percentage of cycles cpu is active system.cpu.activity 95.159695 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -337,72 +338,72 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads
system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 1975 # number of replacements system.cpu.icache.tags.replacements 1975 # number of replacements
system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits
system.cpu.icache.overall_hits::total 48606795 # number of overall hits system.cpu.icache.overall_hits::total 48606790 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses
system.cpu.icache.overall_misses::total 4532 # number of overall misses system.cpu.icache.overall_misses::total 4534 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
@ -411,38 +412,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
@ -458,23 +459,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
@ -499,17 +500,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 286458750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214640250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::total 501099000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 226995250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 274103750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 501099000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
@ -534,17 +535,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -564,17 +565,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
@ -586,51 +587,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 764 # number of replacements system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits
system.cpu.dcache.overall_hits::total 168254256 # number of overall hits system.cpu.dcache.overall_hits::total 168254255 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses
system.cpu.dcache.overall_misses::total 20962 # number of overall misses system.cpu.dcache.overall_misses::total 20963 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
@ -647,19 +648,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -667,12 +668,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu
system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
@ -681,14 +682,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
@ -697,14 +698,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.041672 # Number of seconds simulated sim_seconds 0.041680 # Number of seconds simulated
sim_ticks 41671895000 # Number of ticks simulated sim_ticks 41680207000 # Number of ticks simulated
final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 101828 # Simulator instruction rate (inst/s) host_inst_rate 118687 # Simulator instruction rate (inst/s)
host_op_rate 101828 # Simulator op (including micro ops) rate (op/s) host_op_rate 118687 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46172411 # Simulator tick rate (ticks/s) host_tick_rate 53827332 # Simulator tick rate (ticks/s)
host_mem_usage 228672 # Number of bytes of host memory used host_mem_usage 260144 # Number of bytes of host memory used
host_seconds 902.53 # Real time elapsed on the host host_seconds 774.33 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 178816 # Nu
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 4938 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 316032 # Total number of bytes read from memory system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 443 # Per bank write bursts
system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 270 # Per bank write bursts
system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 295 # Per bank write bursts
system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 499 # Per bank write bursts
system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 209 # Per bank write bursts
system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 212 # Per bank write bursts
system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 207 # Per bank write bursts
system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 265 # Per bank write bursts
system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 219 # Per bank write bursts
system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 249 # Per bank write bursts
system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 238 # Per bank write bursts
system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 236 # Per bank write bursts
system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 379 # Per bank write bursts
system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 325 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 469 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 423 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 41671821000 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 41680133000 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 4938 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 4938 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@ -150,92 +152,83 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation system.physmem.totQLat 34068750 # Total ticks spent queuing
system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation system.physmem.totBankLat 67663750 # Total ticks spent accessing banks
system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst
system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst
system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst
system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.totQLat 20561250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
system.physmem.totBankLat 64336250 # Total cycles spent in bank access
system.physmem.avgQLat 4163.88 # Average queueing delay per request
system.physmem.avgBankLat 13028.81 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22192.69 # Average memory access latency
system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.readRowHits 4578 # Number of row buffer hits during reads system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4195 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8439007.90 # Average gap between requests system.physmem.avgGap 8440691.17 # Average gap between requests
system.membus.throughput 7583816 # Throughput (bytes/s) system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 7582304 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadReq 3216 # Transaction distribution
system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
@ -246,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 316032 # Total data (bytes) system.membus.data_through_bus 316032 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.lookups 13412627 # Number of BP lookups
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
@ -263,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996270 # DTB read hits system.cpu.dtb.read_hits 19996265 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996280 # DTB read accesses system.cpu.dtb.read_accesses 19996275 # DTB read accesses
system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_hits 6501862 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501886 # DTB write accesses system.cpu.dtb.write_accesses 6501885 # DTB write accesses
system.cpu.dtb.data_hits 26498133 # DTB hits system.cpu.dtb.data_hits 26498127 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498166 # DTB accesses system.cpu.dtb.data_accesses 26498160 # DTB accesses
system.cpu.itb.fetch_hits 9956949 # ITB hits system.cpu.itb.fetch_hits 9956950 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 9956998 # ITB accesses system.cpu.itb.fetch_accesses 9956999 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -292,17 +285,17 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 83343791 # number of cpu cycles simulated system.cpu.numCycles 83360415 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.agen_unit.agens 26722393 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
@ -310,16 +303,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 799060
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed.
system.cpu.activity 90.717920 # Percentage of cycles cpu is active system.cpu.activity 90.699835 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed
@ -331,72 +324,72 @@ system.cpu.committedInsts 91903056 # Nu
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads
system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 7635 # number of replacements system.cpu.icache.tags.replacements 7635 # number of replacements
system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
system.cpu.icache.overall_hits::total 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses
system.cpu.icache.overall_misses::total 11398 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@ -405,38 +398,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
@ -452,23 +445,23 @@ system.cpu.toL2Bus.data_through_bus 758400 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
@ -493,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
@ -528,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -558,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
@ -580,51 +573,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits
system.cpu.dcache.overall_hits::total 26488508 # number of overall hits system.cpu.dcache.overall_hits::total 26488450 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses
system.cpu.dcache.overall_misses::total 8793 # number of overall misses system.cpu.dcache.overall_misses::total 8851 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
@ -635,38 +628,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
@ -675,14 +668,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
@ -691,14 +684,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 25046000 # Number of ticks simulated sim_ticks 25485000 # Number of ticks simulated
final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 22373 # Simulator instruction rate (inst/s) host_inst_rate 27492 # Simulator instruction rate (inst/s)
host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) host_op_rate 27490 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 87684145 # Simulator tick rate (ticks/s) host_tick_rate 109632626 # Simulator tick rate (ticks/s)
host_mem_usage 225308 # Number of bytes of host memory used host_mem_usage 225100 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host host_seconds 0.23 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19200 # Nu
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 469 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 29952 # Total number of bytes read from memory system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 65 # Per bank write bursts
system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 29 # Per bank write bursts
system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 27 # Per bank write bursts
system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 41 # Per bank write bursts
system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 19 # Per bank write bursts
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 19 # Per bank write bursts
system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 119 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 46 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 25031500 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 25470500 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 469 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 469 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -150,48 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation
system.physmem.totQLat 1857500 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation
system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
system.physmem.totBusLat 2345000 # Total cycles spent in databus access system.physmem.totQLat 2272250 # Total ticks spent queuing
system.physmem.totBankLat 7617500 # Total cycles spent in bank access system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.avgQLat 3960.55 # Average queueing delay per request system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgBankLat 16242.00 # Average bank access latency per request system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst
system.physmem.avgMemAccLat 25202.56 # Average memory access latency system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst
system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst
system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 9.34 # Data bus utilization in percentage system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtil 9.20 # Data bus utilization in percentage
system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 385 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 53372.07 # Average gap between requests system.physmem.avgGap 54308.10 # Average gap between requests
system.membus.throughput 1195879582 # Throughput (bytes/s) system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1175279576 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadReq 396 # Transaction distribution
system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution
@ -202,10 +210,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29952 # Total data (bytes) system.membus.data_through_bus 29952 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.5 # Layer utilization (%) system.membus.respLayer1.utilization 17.2 # Layer utilization (%)
system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.lookups 1632 # Number of BP lookups
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
@ -248,7 +256,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 50093 # number of cpu cycles simulated system.cpu.numCycles 50971 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
@ -270,12 +278,12 @@ system.cpu.execution_unit.executions 4448 # Nu
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
system.cpu.activity 14.724612 # Percentage of cycles cpu is active system.cpu.activity 14.470974 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed
@ -287,36 +295,36 @@ system.cpu.committedInsts 6390 # Nu
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads
system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
@ -329,12 +337,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
system.cpu.icache.overall_misses::total 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
@ -347,12 +355,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@ -373,26 +381,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
@ -407,21 +415,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -439,17 +447,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
@ -472,17 +480,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -502,17 +510,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
@ -524,27 +532,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
@ -561,14 +569,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
system.cpu.dcache.overall_misses::total 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
@ -585,19 +593,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
@ -617,14 +625,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
@ -633,14 +641,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 24587000 # Number of ticks simulated sim_ticks 24975000 # Number of ticks simulated
final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 52979 # Simulator instruction rate (inst/s) host_inst_rate 84511 # Simulator instruction rate (inst/s)
host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) host_op_rate 84494 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 223940501 # Simulator tick rate (ticks/s) host_tick_rate 362882134 # Simulator tick rate (ticks/s)
host_mem_usage 224928 # Number of bytes of host memory used host_mem_usage 254488 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host host_seconds 0.07 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20288 # Nu
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 455 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 29120 # Total number of bytes read from memory system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 28 # Per bank write bursts
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 0 # Per bank write bursts
system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 0 # Per bank write bursts
system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 0 # Per bank write bursts
system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 8 # Per bank write bursts
system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 3 # Per bank write bursts
system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 12 # Per bank write bursts
system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 51 # Per bank write bursts
system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 59 # Per bank write bursts
system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 75 # Per bank write bursts
system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 36 # Per bank write bursts
system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 19 # Per bank write bursts
system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 52 # Per bank write bursts
system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 28 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 77 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 24519000 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 24894000 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 455 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 455 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@ -150,48 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation
system.physmem.totQLat 2305250 # Total cycles spent in queuing delays system.physmem.totQLat 3167500 # Total ticks spent queuing
system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2275000 # Total cycles spent in databus access system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers
system.physmem.totBankLat 8195000 # Total cycles spent in bank access system.physmem.totBankLat 8112500 # Total ticks spent accessing banks
system.physmem.avgQLat 5066.48 # Average queueing delay per request system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 18010.99 # Average bank access latency per request system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28077.47 # Average memory access latency system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.25 # Data bus utilization in percentage system.physmem.busUtil 9.11 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 348 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 53887.91 # Average gap between requests system.physmem.avgGap 54712.09 # Average gap between requests
system.membus.throughput 1184365722 # Throughput (bytes/s) system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1165965966 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadReq 404 # Transaction distribution
system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution
@ -202,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29120 # Total data (bytes) system.membus.data_through_bus 29120 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.4 # Layer utilization (%) system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
system.cpu.branchPred.lookups 1157 # Number of BP lookups system.cpu.branchPred.lookups 1156 # Number of BP lookups
system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups
system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBHits 339 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -234,14 +240,14 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 49175 # number of cpu cycles simulated system.cpu.numCycles 49951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
@ -256,12 +262,12 @@ system.cpu.execution_unit.executions 3133 # Nu
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
system.cpu.activity 10.946619 # Percentage of cycles cpu is active system.cpu.activity 10.776561 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed
@ -273,36 +279,36 @@ system.cpu.committedInsts 5814 # Nu
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads
system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
@ -315,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
@ -333,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871
system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -359,26 +365,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
@ -393,21 +399,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -425,17 +431,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@ -458,17 +464,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -488,17 +494,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
@ -510,27 +516,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
@ -547,14 +553,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n
system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses
system.cpu.dcache.overall_misses::total 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@ -571,14 +577,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517
system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
@ -603,14 +609,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
@ -619,14 +625,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

831
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
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753
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18469500 # Number of ticks simulated sim_ticks 18905500 # Number of ticks simulated
final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 33738 # Simulator instruction rate (inst/s) host_inst_rate 83485 # Simulator instruction rate (inst/s)
host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) host_op_rate 83467 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 107564291 # Simulator tick rate (ticks/s) host_tick_rate 272386071 # Simulator tick rate (ticks/s)
host_mem_usage 225768 # Number of bytes of host memory used host_mem_usage 250488 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host host_seconds 0.07 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 22080 # Nu
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 446 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 28544 # Total number of bytes read from memory system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 70 # Per bank write bursts
system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 54 # Per bank write bursts
system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 53 # Per bank write bursts
system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 61 # Per bank write bursts
system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 52 # Per bank write bursts
system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 13 # Per bank write bursts
system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 8 # Per bank write bursts
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 2 # Per bank write bursts
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 0 # Per bank write bursts
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 0 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 4 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 0 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 18341000 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 18777000 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 446 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 446 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation
system.physmem.totQLat 1996500 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation
system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation
system.physmem.totBusLat 2230000 # Total cycles spent in databus access system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
system.physmem.totBankLat 6765000 # Total cycles spent in bank access system.physmem.totQLat 3018500 # Total ticks spent queuing
system.physmem.avgQLat 4476.46 # Average queueing delay per request system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.avgBankLat 15168.16 # Average bank access latency per request system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.totBankLat 6710000 # Total ticks spent accessing banks
system.physmem.avgMemAccLat 24644.62 # Average memory access latency system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst
system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.busUtil 12.07 # Data bus utilization in percentage system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.readRowHits 380 # Number of row buffer hits during reads system.physmem.busUtil 11.80 # Data bus utilization in percentage
system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 368 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 41123.32 # Average gap between requests system.physmem.avgGap 42100.90 # Average gap between requests
system.membus.throughput 1545466851 # Throughput (bytes/s) system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1509825183 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadReq 399 # Transaction distribution
system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution
@ -202,10 +211,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 28544 # Total data (bytes) system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 22.7 # Layer utilization (%) system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.lookups 2238 # Number of BP lookups
system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
@ -234,10 +243,10 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 36940 # number of cpu cycles simulated system.cpu.numCycles 37812 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
@ -245,27 +254,27 @@ system.cpu.fetch.Cycles 2263 # Nu
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2098 # Number of cycles decode is running system.cpu.decode.RunCycles 2098 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
@ -275,7 +284,7 @@ system.cpu.decode.BranchMispred 154 # Nu
system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1987 # Number of cycles rename is running system.cpu.rename.RunCycles 1987 # Number of cycles rename is running
@ -298,66 +307,66 @@ system.cpu.memDep0.conflictingLoads 52 # Nu
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
@ -384,21 +393,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8903 # Type of FU issued system.cpu.iq.FU_type_0::total 8904 # Type of FU issued
system.cpu.iq.rate 0.241012 # Inst issue rate system.cpu.iq.rate 0.235481 # Inst issue rate
system.cpu.iq.fu_busy_cnt 171 # FU busy when requested system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
@ -425,43 +434,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_refs 3202 # number of memory reference insts executed
system.cpu.iew.exec_branches 1351 # Number of branches executed system.cpu.iew.exec_branches 1351 # Number of branches executed
system.cpu.iew.exec_stores 1523 # Number of stores executed system.cpu.iew.exec_stores 1524 # Number of stores executed
system.cpu.iew.exec_rate 0.230157 # Inst execution rate system.cpu.iew.exec_rate 0.224876 # Inst execution rate
system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8157 # cumulative count of insts written-back system.cpu.iew.wb_count 8158 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4221 # num instructions producing a value system.cpu.iew.wb_producers 4220 # num instructions producing a value
system.cpu.iew.wb_consumers 6683 # num instructions consuming a value system.cpu.iew.wb_consumers 6682 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -474,22 +483,22 @@ system.cpu.commit.int_insts 5698 # Nu
system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21366 # The number of ROB reads system.cpu.rob.rob_reads 21334 # The number of ROB reads
system.cpu.rob.rob_writes 21446 # The number of ROB writes system.cpu.rob.rob_writes 21446 # The number of ROB writes
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads
system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13474 # number of integer regfile reads system.cpu.int_regfile_reads 13476 # number of integer regfile reads
system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.int_regfile_writes 7049 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
@ -504,19 +513,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
@ -529,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 442 # n
system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
system.cpu.icache.overall_misses::total 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses
@ -547,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243660
system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
@ -573,36 +582,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
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@ -656,17 +665,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 #
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -686,17 +695,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
@ -708,51 +717,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor
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system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
system.cpu.dcache.overall_hits::total 2192 # number of overall hits system.cpu.dcache.overall_hits::total 2188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
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@ -763,20 +772,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2623
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system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
@ -787,12 +796,12 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
@ -801,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
@ -817,14 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887
system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

519
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 20802500 # Number of ticks simulated sim_ticks 20892500 # Number of ticks simulated
final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 86492 # Simulator instruction rate (inst/s) host_inst_rate 70791 # Simulator instruction rate (inst/s)
host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) host_op_rate 70777 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 337526822 # Simulator tick rate (ticks/s) host_tick_rate 277537926 # Simulator tick rate (ticks/s)
host_mem_usage 231936 # Number of bytes of host memory used host_mem_usage 260788 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host host_seconds 0.08 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 423 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 27072 # Total number of bytes read from memory system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 24 # Per bank write bursts
system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 7 # Per bank write bursts
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 1 # Per bank write bursts
system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 8 # Per bank write bursts
system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 0 # Per bank write bursts
system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 78 # Per bank write bursts
system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 80 # Per bank write bursts
system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 62 # Per bank write bursts
system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 35 # Per bank write bursts
system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 18 # Per bank write bursts
system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 10 # Per bank write bursts
system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 52 # Per bank write bursts
system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 12 # Per bank write bursts
system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 21 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 7 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 8 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 20733000 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 20823000 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 423 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 423 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -150,48 +152,53 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation
system.physmem.totQLat 2859500 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation
system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests system.physmem.totQLat 3229250 # Total ticks spent queuing
system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBankLat 6490000 # Total cycles spent in bank access system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6760.05 # Average queueing delay per request system.physmem.totBankLat 6490000 # Total ticks spent accessing banks
system.physmem.avgBankLat 15342.79 # Average bank access latency per request system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst
system.physmem.avgMemAccLat 27102.84 # Average memory access latency system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 10.17 # Data bus utilization in percentage system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.avgRdQLen 0.55 # Average read queue length over time system.physmem.busUtil 10.12 # Data bus utilization in percentage
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads
system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 343 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 49014.18 # Average gap between requests system.physmem.avgGap 49226.95 # Average gap between requests
system.membus.throughput 1301382045 # Throughput (bytes/s) system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1295775996 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadReq 342 # Transaction distribution
system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution
@ -204,8 +211,8 @@ system.membus.data_through_bus 27072 # To
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 18.9 # Layer utilization (%) system.membus.respLayer1.utilization 18.8 # Layer utilization (%)
system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.lookups 1636 # Number of BP lookups
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
@ -216,7 +223,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 41606 # number of cpu cycles simulated system.cpu.numCycles 41786 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
@ -238,12 +245,12 @@ system.cpu.execution_unit.executions 3957 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
system.cpu.activity 15.009854 # Percentage of cycles cpu is active system.cpu.activity 14.945197 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed
@ -255,36 +262,36 @@ system.cpu.committedInsts 5327 # Nu
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads
system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
@ -297,12 +304,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
system.cpu.icache.overall_misses::total 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
@ -315,12 +322,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938
system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,26 +348,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
@ -375,21 +382,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
@ -410,17 +417,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 423 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
@ -443,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -473,17 +480,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@ -495,27 +502,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
@ -532,14 +539,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
@ -556,14 +563,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
@ -588,14 +595,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
@ -604,14 +611,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

1211
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
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1338
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

521
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000027 # Number of seconds simulated sim_seconds 0.000028 # Number of seconds simulated
sim_ticks 27282000 # Number of ticks simulated sim_ticks 27705000 # Number of ticks simulated
final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 96636 # Simulator instruction rate (inst/s) host_inst_rate 72386 # Simulator instruction rate (inst/s)
host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) host_op_rate 72381 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 173854426 # Simulator tick rate (ticks/s) host_tick_rate 132251643 # Simulator tick rate (ticks/s)
host_mem_usage 231852 # Number of bytes of host memory used host_mem_usage 260736 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host host_seconds 0.21 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19072 # Nu
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 436 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 27904 # Total number of bytes read from memory system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 97 # Per bank write bursts
system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 28 # Per bank write bursts
system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 38 # Per bank write bursts
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 20 # Per bank write bursts
system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 16 # Per bank write bursts
system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 29 # Per bank write bursts
system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 32 # Per bank write bursts
system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 4 # Per bank write bursts
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 48 # Per bank write bursts
system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 58 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 33 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 27248500 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 27671500 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 436 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 436 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation
system.physmem.totQLat 1525500 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation
system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation
system.physmem.totBusLat 2180000 # Total cycles spent in databus access system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
system.physmem.totBankLat 6325000 # Total cycles spent in bank access system.physmem.totQLat 2393750 # Total ticks spent queuing
system.physmem.avgQLat 3498.85 # Average queueing delay per request system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.avgBankLat 14506.88 # Average bank access latency per request system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.totBankLat 6256250 # Total ticks spent accessing banks
system.physmem.avgMemAccLat 23005.73 # Average memory access latency system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst
system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.busUtil 7.99 # Data bus utilization in percentage system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen 0.37 # Average read queue length over time system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.busUtil 7.87 # Data bus utilization in percentage
system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 372 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 62496.56 # Average gap between requests system.physmem.avgGap 63466.74 # Average gap between requests
system.membus.throughput 1020453046 # Throughput (bytes/s) system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1004872767 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadReq 351 # Transaction distribution
system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution
@ -204,8 +213,8 @@ system.membus.data_through_bus 27840 # To
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 14.9 # Layer utilization (%) system.membus.respLayer1.utilization 14.6 # Layer utilization (%)
system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.lookups 5146 # Number of BP lookups
system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
@ -216,7 +225,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 54565 # number of cpu cycles simulated system.cpu.numCycles 55411 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
@ -238,12 +247,12 @@ system.cpu.execution_unit.executions 11045 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
system.cpu.activity 32.196463 # Percentage of cycles cpu is active system.cpu.activity 31.704896 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed
@ -255,36 +264,36 @@ system.cpu.committedInsts 15162 # Nu
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads
system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
@ -297,12 +306,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
system.cpu.icache.overall_misses::total 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
@ -315,12 +324,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,26 +350,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
@ -375,21 +384,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -407,17 +416,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
@ -440,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -470,17 +479,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
@ -492,27 +501,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
@ -531,14 +540,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
system.cpu.dcache.overall_misses::total 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@ -557,14 +566,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
@ -589,14 +598,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
@ -605,14 +614,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

656
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000027 # Number of seconds simulated sim_seconds 0.000027 # Number of seconds simulated
sim_ticks 26524500 # Number of ticks simulated sim_ticks 26616500 # Number of ticks simulated
final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 19767 # Simulator instruction rate (inst/s) host_inst_rate 75478 # Simulator instruction rate (inst/s)
host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) host_op_rate 75473 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36317578 # Simulator tick rate (ticks/s) host_tick_rate 139143595 # Simulator tick rate (ticks/s)
host_mem_usage 236084 # Number of bytes of host memory used host_mem_usage 260732 # Number of bytes of host memory used
host_seconds 0.73 # Real time elapsed on the host host_seconds 0.19 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 21440 # Nu
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 482 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 482 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 30848 # Total number of bytes read from memory system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 102 # Per bank write bursts
system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 29 # Per bank write bursts
system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 50 # Per bank write bursts
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 19 # Per bank write bursts
system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 35 # Per bank write bursts
system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 4 # Per bank write bursts
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 61 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 36 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.totGap 26363500 # Total gap between requests system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.totGap 26455500 # Total gap between requests
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::6 482 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.readPktSize::6 482 # Read request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@ -150,47 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation
system.physmem.totQLat 1755500 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation
system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation
system.physmem.totBusLat 2410000 # Total cycles spent in databus access system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation
system.physmem.totBankLat 6765000 # Total cycles spent in bank access system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
system.physmem.avgQLat 3642.12 # Average queueing delay per request system.physmem.totQLat 2423000 # Total ticks spent queuing
system.physmem.avgBankLat 14035.27 # Average bank access latency per request system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
system.physmem.avgMemAccLat 22677.39 # Average memory access latency system.physmem.totBankLat 6778750 # Total ticks spent accessing banks
system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst
system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.busUtil 9.09 # Data bus utilization in percentage system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdQLen 0.41 # Average read queue length over time system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.readRowHits 430 # Number of row buffer hits during reads system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.05 # Data bus utilization in percentage
system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 413 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 54696.06 # Average gap between requests system.physmem.avgGap 54886.93 # Average gap between requests
system.membus.throughput 1163000245 # Throughput (bytes/s) system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1158980332 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadReq 399 # Transaction distribution
system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution
@ -201,63 +211,63 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 30848 # Total data (bytes) system.membus.data_through_bus 30848 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.0 # Layer utilization (%) system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
system.cpu.branchPred.lookups 6716 # Number of BP lookups system.cpu.branchPred.lookups 6713 # Number of BP lookups
system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups
system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBHits 2432 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 53050 # number of cpu cycles simulated system.cpu.numCycles 53234 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8344 # Number of cycles decode is running system.cpu.decode.RunCycles 8343 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.RunCycles 7952 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename
@ -282,15 +292,15 @@ system.cpu.iq.iqSquashedInstsIssued 97 # Nu
system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
@ -298,7 +308,7 @@ system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
@ -368,10 +378,10 @@ system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Ty
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21122 # Type of FU issued system.cpu.iq.FU_type_0::total 21122 # Type of FU issued
system.cpu.iq.rate 0.398153 # Inst issue rate system.cpu.iq.rate 0.396776 # Inst issue rate
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
@ -412,35 +422,35 @@ system.cpu.iew.exec_nop 1134 # nu
system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_branches 4239 # Number of branches executed
system.cpu.iew.exec_stores 2022 # Number of stores executed system.cpu.iew.exec_stores 2022 # Number of stores executed
system.cpu.iew.exec_rate 0.378398 # Inst execution rate system.cpu.iew.exec_rate 0.377090 # Inst execution rate
system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19522 # cumulative count of insts written-back system.cpu.iew.wb_count 19522 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9120 # num instructions producing a value system.cpu.iew.wb_producers 9120 # num instructions producing a value
system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_consumers 11235 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -453,22 +463,22 @@ system.cpu.commit.int_insts 12174 # Nu
system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 54596 # The number of ROB reads system.cpu.rob.rob_reads 54530 # The number of ROB reads
system.cpu.rob.rob_writes 50298 # The number of ROB writes system.cpu.rob.rob_writes 50298 # The number of ROB writes
system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads
system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_reads 32043 # number of integer regfile reads
system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.int_regfile_writes 17841 # number of integer regfile writes
system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_reads 6919 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
@ -483,55 +493,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
system.cpu.icache.overall_hits::total 4873 # number of overall hits system.cpu.icache.overall_hits::total 4872 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses
system.cpu.icache.overall_misses::total 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -552,36 +562,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337
system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -599,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
system.cpu.l2cache.overall_misses::total 482 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
@ -632,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -662,17 +672,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
@ -684,27 +694,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
@ -723,14 +733,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
system.cpu.dcache.overall_misses::total 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@ -749,14 +759,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
@ -781,14 +791,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
@ -797,14 +807,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450
system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

3800
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
View file

File diff suppressed because it is too large Load diff

352
tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
View file

@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
sim_ticks 100000000000 # Number of ticks simulated sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 12102739985 # Simulator tick rate (ticks/s) host_tick_rate 20181472495 # Simulator tick rate (ticks/s)
host_mem_usage 228608 # Number of bytes of host memory used host_mem_usage 192916 # Number of bytes of host memory used
host_seconds 8.26 # Real time elapsed on the host host_seconds 4.96 # Real time elapsed on the host
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
@ -15,77 +15,79 @@ system.physmem.bw_read::cpu 2133311360 # To
system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller system.physmem.readReqs 3333300 # Number of read requests accepted
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesRead 213331136 # Total number of bytes read from memory system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM
system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis system.physmem.perBankRdBursts::0 217600 # Per bank write bursts
system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis system.physmem.perBankRdBursts::1 217600 # Per bank write bursts
system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis system.physmem.perBankRdBursts::2 217600 # Per bank write bursts
system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::3 217600 # Per bank write bursts
system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::4 210100 # Per bank write bursts
system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::5 204800 # Per bank write bursts
system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::6 204800 # Per bank write bursts
system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::7 204800 # Per bank write bursts
system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::8 204800 # Per bank write bursts
system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::9 204800 # Per bank write bursts
system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::10 204800 # Per bank write bursts
system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::11 204800 # Per bank write bursts
system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::12 204800 # Per bank write bursts
system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis system.physmem.perBankRdBursts::13 204800 # Per bank write bursts
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::14 204800 # Per bank write bursts
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankRdBursts::15 204800 # Per bank write bursts
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 99999960000 # Total gap between requests system.physmem.totGap 99999960000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 3333300 # Categorize read packet sizes system.physmem.readPktSize::6 3333300 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
@ -138,35 +140,135 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation
system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation
system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation
system.physmem.totBusLat 16666500000 # Total cycles spent in databus access system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation
system.physmem.totBankLat 45939671250 # Total cycles spent in bank access system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation
system.physmem.avgQLat 383.63 # Average queueing delay per request system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation
system.physmem.avgBankLat 13782.04 # Average bank access latency per request system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation
system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation
system.physmem.avgMemAccLat 19165.67 # Average memory access latency system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation
system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation
system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation
system.physmem.totQLat 27766345550 # Total ticks spent queuing
system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers
system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks
system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtil 16.67 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.64 # Average read queue length over time system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads
system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.readRowHits 3307200 # Number of row buffer hits during reads system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 3294382 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 30000.29 # Average gap between requests system.physmem.avgGap 30000.29 # Average gap between requests
system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.throughput 2133311360 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
@ -177,7 +279,7 @@ system.membus.tot_pkt_size::total 213331136 # Cu
system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.data_through_bus 213331136 # Total data (bytes)
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 17.2 # Layer utilization (%) system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
@ -231,8 +333,8 @@ system.monitor.writeBurstLengthHist::19 0 # Hi
system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
@ -284,20 +386,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.totalWrittenBytes 0 # Number of bytes written
system.monitor.readLatencyHist::samples 3333299 # Read request-response latency system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency
system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency
system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency
system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency
system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency
system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency
system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency
system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency
system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency
system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency
system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency
system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency
system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency
system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency
system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
@ -418,17 +520,17 @@ system.monitor.ittReqReq::min_value 30000 # Re
system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time
system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions
system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions
system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions
system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions