This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
624 lines
72 KiB
Text
624 lines
72 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000021 # Number of seconds simulated
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sim_ticks 20892500 # Number of ticks simulated
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final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 70791 # Simulator instruction rate (inst/s)
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host_op_rate 70777 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 277537926 # Simulator tick rate (ticks/s)
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host_mem_usage 260788 # Number of bytes of host memory used
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host_seconds 0.08 # Real time elapsed on the host
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 423 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 24 # Per bank write bursts
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system.physmem.perBankRdBursts::1 7 # Per bank write bursts
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system.physmem.perBankRdBursts::2 1 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8 # Per bank write bursts
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system.physmem.perBankRdBursts::4 0 # Per bank write bursts
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system.physmem.perBankRdBursts::5 78 # Per bank write bursts
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system.physmem.perBankRdBursts::6 80 # Per bank write bursts
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system.physmem.perBankRdBursts::7 62 # Per bank write bursts
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system.physmem.perBankRdBursts::8 35 # Per bank write bursts
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system.physmem.perBankRdBursts::9 18 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10 # Per bank write bursts
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system.physmem.perBankRdBursts::11 52 # Per bank write bursts
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system.physmem.perBankRdBursts::12 12 # Per bank write bursts
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system.physmem.perBankRdBursts::13 21 # Per bank write bursts
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system.physmem.perBankRdBursts::14 7 # Per bank write bursts
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system.physmem.perBankRdBursts::15 8 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 20823000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 423 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation
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system.physmem.totQLat 3229250 # Total ticks spent queuing
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system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 6490000 # Total ticks spent accessing banks
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system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 10.12 # Data bus utilization in percentage
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system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 343 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 49226.95 # Average gap between requests
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system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 1295775996 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 342 # Transaction distribution
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system.membus.trans_dist::ReadResp 342 # Transaction distribution
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system.membus.trans_dist::ReadExReq 81 # Transaction distribution
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system.membus.trans_dist::ReadExResp 81 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 27072 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 18.8 # Layer utilization (%)
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system.cpu.branchPred.lookups 1636 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 584 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 41786 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 1472 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3957 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
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system.cpu.activity 14.945197 # Percentage of cycles cpu is active
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system.cpu.comLoads 715 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1115 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2526 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
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system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 892 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 914 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|