ccfdc533b9
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
1523 lines
177 KiB
Text
1523 lines
177 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.631415 # Number of seconds simulated
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sim_ticks 2631415171500 # Number of ticks simulated
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final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 471038 # Simulator instruction rate (inst/s)
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host_op_rate 599389 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 20585916294 # Simulator tick rate (ticks/s)
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host_mem_usage 424736 # Number of bytes of host memory used
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host_seconds 127.83 # Real time elapsed on the host
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sim_insts 60210883 # Number of instructions simulated
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sim_ops 76617506 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory
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system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15690904 # Number of read requests accepted
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system.physmem.writeReqs 811702 # Number of write requests accepted
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system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 980392 # Per bank write bursts
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system.physmem.perBankRdBursts::1 980205 # Per bank write bursts
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system.physmem.perBankRdBursts::2 980222 # Per bank write bursts
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system.physmem.perBankRdBursts::3 980428 # Per bank write bursts
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system.physmem.perBankRdBursts::4 986950 # Per bank write bursts
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system.physmem.perBankRdBursts::5 980709 # Per bank write bursts
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system.physmem.perBankRdBursts::6 980611 # Per bank write bursts
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system.physmem.perBankRdBursts::7 980420 # Per bank write bursts
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system.physmem.perBankRdBursts::8 980615 # Per bank write bursts
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system.physmem.perBankRdBursts::9 980431 # Per bank write bursts
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system.physmem.perBankRdBursts::10 979815 # Per bank write bursts
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system.physmem.perBankRdBursts::11 979555 # Per bank write bursts
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system.physmem.perBankRdBursts::12 980153 # Per bank write bursts
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system.physmem.perBankRdBursts::13 980095 # Per bank write bursts
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system.physmem.perBankRdBursts::14 980165 # Per bank write bursts
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system.physmem.perBankRdBursts::15 980109 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6734 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6600 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6608 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6671 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6747 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7057 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7034 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6884 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7000 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6825 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6323 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6129 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6612 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6395 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6622 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6616 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2631410752000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 6700 # Read request sizes (log2)
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system.physmem.readPktSize::3 15532032 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 152172 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754038 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 57664 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation
|
|
system.physmem.totQLat 377292466250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.00 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 15616441 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 91020 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 159454.26 # Average gap between requests
|
|
system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 54391586 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16743633 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16743633 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763392 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763392 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 57664 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 131346 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131346 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 143126845 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
|
system.l2c.tags.replacements 62057 # number of replacements
|
|
system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 596380 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 239908 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 244991 # number of overall hits
|
|
system.l2c.overall_hits::total 1356485 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 3942 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 5224 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 6651 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 5006 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 20826 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1375 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1512 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2887 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 69398 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 63578 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 3942 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 74622 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 6651 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 68584 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 153802 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 3942 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 74622 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 6651 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 68584 # number of overall misses
|
|
system.l2c.overall_misses::total 153802 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 279121500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 387849000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 474818500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 382257500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1524285750 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 256989 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 208991 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 4923800203 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4505788417 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 9429588620 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 279121500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 5311649203 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 474818500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 4888045917 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 10953874370 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 279121500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 5311649203 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 474818500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 4888045917 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 10953874370 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9914 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3651 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 419253 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 188436 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 10009 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 3517 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 435838 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 192148 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1262766 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 596380 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 596380 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1389 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1524 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2913 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 126094 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 121427 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 247521 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 9914 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 3651 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 419253 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 314530 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 10009 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 3517 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 435838 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 313575 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1510287 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 9914 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 3651 # number of overall (read+write) accesses
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|
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|
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|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 52751818 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 138642313 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 48128720 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8167 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 126646645 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7352406 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6766 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5599485 # DTB write hits
|
|
system.cpu0.dtb.write_misses 1847 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7359172 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5601332 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 12951891 # DTB hits
|
|
system.cpu0.dtb.misses 8613 # DTB misses
|
|
system.cpu0.dtb.accesses 12960504 # DTB accesses
|
|
system.cpu0.itb.inst_hits 30170189 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3579 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses
|
|
system.cpu0.itb.hits 30170189 # DTB hits
|
|
system.cpu0.itb.misses 3579 # DTB misses
|
|
system.cpu0.itb.accesses 30173768 # DTB accesses
|
|
system.cpu0.numCycles 2629696361 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 29597158 # Number of instructions committed
|
|
system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1050225 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 33970200 # number of integer instructions
|
|
system.cpu0.num_fp_insts 4584 # number of float instructions
|
|
system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 13522491 # number of memory refs
|
|
system.cpu0.num_load_insts 7673972 # Number of load instructions
|
|
system.cpu0.num_store_insts 5848519 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed
|
|
system.cpu0.icache.tags.replacements 856199 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 60648231 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 856712 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013921 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013937 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013921 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013937 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.045005 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 420001 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 436711 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 856712 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 420001 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 436711 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 856712 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 420001 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 436711 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 856712 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869726500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5221934000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10091660500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869726500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5221934000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 10091660500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869726500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5221934000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 10091660500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.525091 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 627593 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 4964348 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 5010385 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 9974733 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118524 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117664 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 236188 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124634 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123125 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247759 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 11417305 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 11756165 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 23173470 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 11417305 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 11756165 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 23173470 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 182326 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 186686 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 369012 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 127483 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 309809 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 309637 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 619446 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 309809 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 309637 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 619446 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2717177250 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2764634500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5481811750 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5932563172 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5512471095 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 11445034267 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81881250 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78503500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 160384750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 8649740422 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 8277105595 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 16926846017 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 8649740422 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 8277105595 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 16926846017 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6635283 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6932466 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 13567749 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5091831 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5133336 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10225167 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124634 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123126 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 247760 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124634 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123125 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247759 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 11727114 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 12065802 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 23792916 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 11727114 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 12065802 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 23792916 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027478 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026929 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.027198 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025037 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023951 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049024 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044361 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046706 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026418 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025662 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026418 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025662 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.851212 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14809.008174 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14855.375299 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46536.112046 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44834.699148 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45700.800478 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13401.186579 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14372.665690 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 596380 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 7647205 # DTB read hits
|
|
system.cpu1.dtb.read_misses 7298 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5633094 # DTB write hits
|
|
system.cpu1.dtb.write_misses 1843 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 7654503 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5634937 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 13280299 # DTB hits
|
|
system.cpu1.dtb.misses 9141 # DTB misses
|
|
system.cpu1.dtb.accesses 13289440 # DTB accesses
|
|
system.cpu1.itb.inst_hits 31334771 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 3728 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses
|
|
system.cpu1.itb.hits 31334771 # DTB hits
|
|
system.cpu1.itb.misses 3728 # DTB misses
|
|
system.cpu1.itb.accesses 31338499 # DTB accesses
|
|
system.cpu1.numCycles 2633133982 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 30613725 # Number of instructions committed
|
|
system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 1090107 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 34913201 # number of integer instructions
|
|
system.cpu1.num_fp_insts 5685 # number of float instructions
|
|
system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 13877284 # number of memory refs
|
|
system.cpu1.num_load_insts 7989860 # Number of load instructions
|
|
system.cpu1.num_store_insts 5887424 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|