ccfdc533b9
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
890 lines
101 KiB
Plaintext
890 lines
101 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000017 # Number of seconds simulated
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sim_ticks 16981000 # Number of ticks simulated
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final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 59313 # Simulator instruction rate (inst/s)
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host_op_rate 73997 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 219275591 # Simulator tick rate (ticks/s)
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host_mem_usage 240508 # Number of bytes of host memory used
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host_seconds 0.08 # Real time elapsed on the host
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sim_insts 4591 # Number of instructions simulated
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sim_ops 5729 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25088 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 392 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 86 # Per bank write bursts
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system.physmem.perBankRdBursts::1 46 # Per bank write bursts
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system.physmem.perBankRdBursts::2 20 # Per bank write bursts
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system.physmem.perBankRdBursts::3 42 # Per bank write bursts
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system.physmem.perBankRdBursts::4 17 # Per bank write bursts
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system.physmem.perBankRdBursts::5 34 # Per bank write bursts
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system.physmem.perBankRdBursts::6 35 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10 # Per bank write bursts
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system.physmem.perBankRdBursts::8 4 # Per bank write bursts
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system.physmem.perBankRdBursts::9 7 # Per bank write bursts
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system.physmem.perBankRdBursts::10 28 # Per bank write bursts
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system.physmem.perBankRdBursts::11 42 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9 # Per bank write bursts
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system.physmem.perBankRdBursts::13 6 # Per bank write bursts
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system.physmem.perBankRdBursts::14 0 # Per bank write bursts
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system.physmem.perBankRdBursts::15 6 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 16923500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 392 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation
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system.physmem.totQLat 3153000 # Total ticks spent queuing
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system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 5403750 # Total ticks spent accessing banks
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system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 11.54 # Data bus utilization in percentage
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system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 332 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 43172.19 # Average gap between requests
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system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 1473647017 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 351 # Transaction distribution
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system.membus.trans_dist::ReadResp 350 # Transaction distribution
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system.membus.trans_dist::ReadExReq 41 # Transaction distribution
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system.membus.trans_dist::ReadExResp 41 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 25024 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
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system.cpu.branchPred.lookups 2481 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 697 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 33963 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
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system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
|
system.cpu.iq.rate 0.262668 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.250950 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2138 # Number of memory references committed
|
|
system.cpu.commit.loads 1200 # Number of loads committed
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1007 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 23234 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
|
system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 2977 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 4 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1584 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2373 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|