ccfdc533b9
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
821 lines
94 KiB
Plaintext
821 lines
94 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000027 # Number of seconds simulated
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sim_ticks 26616500 # Number of ticks simulated
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final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 75478 # Simulator instruction rate (inst/s)
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host_op_rate 75473 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 139143595 # Simulator tick rate (ticks/s)
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host_mem_usage 260732 # Number of bytes of host memory used
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host_seconds 0.19 # Real time elapsed on the host
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sim_insts 14436 # Number of instructions simulated
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sim_ops 14436 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 482 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 102 # Per bank write bursts
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system.physmem.perBankRdBursts::1 29 # Per bank write bursts
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system.physmem.perBankRdBursts::2 50 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24 # Per bank write bursts
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system.physmem.perBankRdBursts::4 19 # Per bank write bursts
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system.physmem.perBankRdBursts::5 0 # Per bank write bursts
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system.physmem.perBankRdBursts::6 32 # Per bank write bursts
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system.physmem.perBankRdBursts::7 35 # Per bank write bursts
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system.physmem.perBankRdBursts::8 4 # Per bank write bursts
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system.physmem.perBankRdBursts::9 1 # Per bank write bursts
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system.physmem.perBankRdBursts::10 1 # Per bank write bursts
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system.physmem.perBankRdBursts::11 0 # Per bank write bursts
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system.physmem.perBankRdBursts::12 57 # Per bank write bursts
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system.physmem.perBankRdBursts::13 31 # Per bank write bursts
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system.physmem.perBankRdBursts::14 61 # Per bank write bursts
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system.physmem.perBankRdBursts::15 36 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 26455500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 482 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
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system.physmem.totQLat 2423000 # Total ticks spent queuing
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system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 6778750 # Total ticks spent accessing banks
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system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 9.05 # Data bus utilization in percentage
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system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 413 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 54886.93 # Average gap between requests
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system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 1158980332 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 399 # Transaction distribution
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system.membus.trans_dist::ReadResp 399 # Transaction distribution
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system.membus.trans_dist::ReadExReq 83 # Transaction distribution
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system.membus.trans_dist::ReadExResp 83 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 30848 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
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system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
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system.cpu.branchPred.lookups 6713 # Number of BP lookups
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system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 2432 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 53234 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 8343 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 7952 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename
|
|
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups
|
|
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 21122 # Type of FU issued
|
|
system.cpu.iq.rate 0.396776 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1134 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 4239 # Number of branches executed
|
|
system.cpu.iew.exec_stores 2022 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.377090 # Inst execution rate
|
|
system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 19522 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 9120 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 11235 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
|
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 3673 # Number of memory references committed
|
|
system.cpu.commit.loads 2225 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 3358 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 54530 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 50298 # The number of ROB writes
|
|
system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
|
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
|
|
system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 32043 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 17841 # number of integer regfile writes
|
|
system.cpu.misc_regfile_reads 6919 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4872 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 507 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 482 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 3995 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 535 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|