stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
This commit is contained in:
Andreas Hansson
parent
646c4a23ca
commit
b63631536d
87 changed files with 16959 additions and 17850 deletions
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@ -520,8 +520,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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writeBursts++;
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// see if we can merge with an existing item in the write
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// queue and keep track of whether we have merged or not, as
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// there is only ever one item to merge with
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// queue and keep track of whether we have merged or not so we
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// can stop at that point and also avoid enqueueing a new
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// request
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bool merged = false;
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auto w = writeQueue.begin();
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@ -529,6 +530,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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// either of the two could be first, if they are the same
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// it does not matter which way we go
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if ((*w)->addr >= addr) {
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// the existing one starts after the new one, figure
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// out where the new one ends with respect to the
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// existing one
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if ((addr + size) >= ((*w)->addr + (*w)->size)) {
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// check if the existing one is completely
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// subsumed in the new one
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@ -550,6 +554,9 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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(*w)->size = (*w)->addr + (*w)->size - addr;
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}
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} else {
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// the new one starts after the current one, figure
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// out where the existing one ends with respect to the
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// new one
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if (((*w)->addr + (*w)->size) >= (addr + size)) {
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// check if the new one is completely subsumed in the
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// existing one
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File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 1.860201 # Nu
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sim_ticks 1860200687500 # Number of ticks simulated
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final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 112423 # Simulator instruction rate (inst/s)
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host_op_rate 112423 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3947369845 # Simulator tick rate (ticks/s)
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host_mem_usage 310252 # Number of bytes of host memory used
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host_seconds 471.25 # Real time elapsed on the host
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host_inst_rate 95880 # Simulator instruction rate (inst/s)
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host_op_rate 95880 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3366492305 # Simulator tick rate (ticks/s)
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host_mem_usage 308824 # Number of bytes of host memory used
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host_seconds 552.56 # Real time elapsed on the host
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sim_insts 52979577 # Number of instructions simulated
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sim_ops 52979577 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
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@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 518206 # To
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system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 445243 # Total number of read requests seen
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system.physmem.writeReqs 117437 # Total number of write requests seen
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system.physmem.cpureqs 562856 # Reqs generatd by CPU via cache - shady
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system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 28495552 # Total number of bytes read from memory
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system.physmem.bytesWritten 7515968 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 55 # Number of read reqs serviced by write Q
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system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis
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@ -336,17 +337,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_respo
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.physmem.port 1008832 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.physmem.port 36011520 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 36055668 # Total data (bytes)
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system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
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@ -819,19 +815,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
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system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
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@ -848,19 +831,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
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system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.data_through_bus 2705756 # Total data (bytes)
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system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
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@ -905,12 +875,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 66 #
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system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2019865 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3677460 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count 5697325 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64631872 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 143567348 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size 208199220 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes)
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system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes)
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system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks)
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@ -4,11 +4,11 @@ sim_seconds 1.842705 # Nu
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sim_ticks 1842705252000 # Number of ticks simulated
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final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 221595 # Simulator instruction rate (inst/s)
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host_op_rate 221595 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5621199023 # Simulator tick rate (ticks/s)
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host_mem_usage 308252 # Number of bytes of host memory used
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host_seconds 327.81 # Real time elapsed on the host
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host_inst_rate 308319 # Simulator instruction rate (inst/s)
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host_op_rate 308319 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7821132493 # Simulator tick rate (ticks/s)
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host_mem_usage 307864 # Number of bytes of host memory used
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host_seconds 235.61 # Real time elapsed on the host
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sim_insts 72641883 # Number of instructions simulated
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sim_ops 72641883 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
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@ -58,14 +58,15 @@ system.physmem.bw_total::cpu1.data 1242973 # To
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system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 99238 # Total number of read requests seen
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system.physmem.writeReqs 44800 # Total number of write requests seen
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system.physmem.cpureqs 144082 # Reqs generatd by CPU via cache - shady
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system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 6351232 # Total number of bytes read from memory
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system.physmem.bytesWritten 2867200 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
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system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis
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@ -298,17 +299,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio
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system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.bridge.slave 13322 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.physmem.port 243525 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.physmem.port 9218432 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 35966088 # Total data (bytes)
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system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
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@ -780,10 +776,10 @@ system.cpu0.num_fp_register_writes 89168 # nu
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system.cpu0.num_mem_refs 8444409 # number of memory refs
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system.cpu0.num_load_insts 4931349 # Number of load instructions
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system.cpu0.num_store_insts 3513060 # Number of store instructions
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system.cpu0.num_idle_cycles 212988700365.392029 # Number of idle cycles
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system.cpu0.num_busy_cycles -212060383474.392029 # Number of busy cycles
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system.cpu0.not_idle_fraction -228.435339 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 229.435339 # Percentage of idle cycles
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system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles
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system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles
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system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed
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system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed
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@ -912,12 +908,12 @@ system.toL2Bus.trans_dist::UpgradeResp 17 # Tr
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system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution
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system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution
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system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution
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system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 849315 # Packet count per connected master and slave (bytes)
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system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1370344 # Packet count per connected master and slave (bytes)
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system.toL2Bus.pkt_count 2219659 # Packet count per connected master and slave (bytes)
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system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27177600 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55325386 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.tot_pkt_size 82502986 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 203464200 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks)
|
||||
|
|
@ -942,13 +938,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
|
|||
system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -959,13 +948,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2707184 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
|
||||
|
|
@ -1412,10 +1394,10 @@ system.cpu1.num_fp_register_writes 24577 # nu
|
|||
system.cpu1.num_mem_refs 2116682 # number of memory refs
|
||||
system.cpu1.num_load_insts 1209934 # Number of load instructions
|
||||
system.cpu1.num_store_insts 906748 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles -715527638.238183 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 1669158056.238183 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 1.750320 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction -0.750320 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 5.133763 # Nu
|
|||
sim_ticks 5133762710000 # Number of ticks simulated
|
||||
final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 199223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 393808 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2508257843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 730904 # Number of bytes of host memory used
|
||||
host_seconds 2046.74 # Real time elapsed on the host
|
||||
host_inst_rate 156198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 308758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1966557914 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 728732 # Number of bytes of host memory used
|
||||
host_seconds 2610.53 # Real time elapsed on the host
|
||||
sim_insts 407759186 # Number of instructions simulated
|
||||
sim_ops 806023868 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory
|
||||
|
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To
|
|||
system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 222526 # Total number of read requests seen
|
||||
system.physmem.writeReqs 148565 # Total number of write requests seen
|
||||
system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 14241664 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 9508160 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis
|
||||
|
|
@ -401,39 +402,31 @@ system.membus.trans_dist::MessageReq 1642 # Tr
|
|||
system.membus.trans_dist::MessageResp 1642 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25548207 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -575,26 +568,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -619,26 +592,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 3276058 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks)
|
||||
|
|
@ -968,16 +921,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.304405 # Nu
|
|||
sim_ticks 5304405061000 # Number of ticks simulated
|
||||
final_tick 5304405061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 226332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 434274 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11093442301 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 870272 # Number of bytes of host memory used
|
||||
host_seconds 478.16 # Real time elapsed on the host
|
||||
host_inst_rate 96456 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185076 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4727720712 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 825708 # Number of bytes of host memory used
|
||||
host_seconds 1121.98 # Real time elapsed on the host
|
||||
sim_insts 108221987 # Number of instructions simulated
|
||||
sim_ops 207651289 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory
|
||||
|
|
@ -72,14 +72,15 @@ system.physmem.bw_total::cpu1.itb.walker 7758 # To
|
|||
system.physmem.bw_total::cpu1.inst 32140877 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 9555659 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 225885267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 804 # Total number of read requests seen
|
||||
system.physmem.writeReqs 46736 # Total number of write requests seen
|
||||
system.physmem.cpureqs 47256 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 51456 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
@ -308,29 +309,6 @@ system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupt
|
|||
system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.physmem.port 95080 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1372 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.i_dont_exist.pio 33352 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.com_1.pio 26412 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.pio 751802 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu0.interrupts.int_slave 2728 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.cpu1.interrupts.int_slave 2670 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.pkt_count::total 1908880 # Packet count per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -371,58 +349,35 @@ system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interr
|
|||
system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 16676 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.com_1.pio 13206 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1503598 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 5456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 5340 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.tot_pkt_size::total 5087902 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.piobus.data_through_bus 5087902 # Total data (bytes)
|
||||
system.piobus.reqLayer0.occupancy 421716677 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer0.occupancy 49000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer1.occupancy 49000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer2.occupancy 7500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer3.occupancy 10159500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer3.occupancy 140500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer4.occupancy 1061000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer5.occupancy 1061000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer5.occupancy 97000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer6.occupancy 97000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer6.occupancy 57000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer7.occupancy 57000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer7.occupancy 30437500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer8.occupancy 30437500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer9.occupancy 586857000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer9.occupancy 1329000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer10.occupancy 1329000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer10.occupancy 33375500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer11.occupancy 33375500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer12.occupancy 23058500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer13.occupancy 23058500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -430,15 +385,15 @@ system.piobus.reqLayer15.occupancy 10500 # La
|
|||
system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer17.occupancy 473807500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer18.occupancy 473807500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer18.occupancy 3197816 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer19.occupancy 3197816 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer19.occupancy 8805500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer20.occupancy 8805500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer20.occupancy 3140084 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer21.occupancy 3140084 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer21.occupancy 421716677 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
||||
system.piobus.reqLayer22.occupancy 1081500 # Layer occupancy (ticks)
|
||||
system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.139589 # Nu
|
|||
sim_ticks 5139589353000 # Number of ticks simulated
|
||||
final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 286755 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 569759 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6048900638 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 936564 # Number of bytes of host memory used
|
||||
host_seconds 849.67 # Real time elapsed on the host
|
||||
host_inst_rate 190335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 378180 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4014985901 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 934028 # Number of bytes of host memory used
|
||||
host_seconds 1280.10 # Real time elapsed on the host
|
||||
sim_insts 243647713 # Number of instructions simulated
|
||||
sim_ops 484108731 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory
|
||||
|
|
@ -70,14 +70,15 @@ system.physmem.bw_total::cpu2.itb.walker 12 # To
|
|||
system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 96603 # Total number of read requests seen
|
||||
system.physmem.writeReqs 74912 # Total number of write requests seen
|
||||
system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 96603 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 74912 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 96603 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 74912 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 6182592 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4794368 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 12 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis
|
||||
|
|
@ -388,39 +389,31 @@ system.membus.trans_dist::MessageReq 216 # Tr
|
|||
system.membus.trans_dist::MessageResp 216 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 32713165 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 164366000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 314753000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 432000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 793885999 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -947,16 +940,16 @@ system.toL2Bus.trans_dist::UpgradeReq 745 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 966317 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3599461 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 26176 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 114965 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 4706919 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 30921472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118979348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 89784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 413728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 150404332 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 267998065 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks)
|
||||
|
|
@ -997,22 +990,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -1033,22 +1010,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 6479664 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks)
|
||||
|
|
@ -1107,10 +1068,10 @@ system.cpu0.num_fp_register_writes 0 # nu
|
|||
system.cpu0.num_mem_refs 14736464 # number of memory refs
|
||||
system.cpu0.num_load_insts 10677140 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4059324 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles
|
||||
system.cpu0.num_idle_cycles 1727957342.597034 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 93395662.402966 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.051278 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.948722 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 847048 # number of replacements
|
||||
|
|
@ -1447,10 +1408,10 @@ system.cpu1.num_fp_register_writes 0 # nu
|
|||
system.cpu1.num_mem_refs 4252332 # number of memory refs
|
||||
system.cpu1.num_load_insts 2649427 # Number of load instructions
|
||||
system.cpu1.num_store_insts 1602905 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 2479239642.942777 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 126766142.057223 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.048644 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.951356 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu2.branchPred.lookups 28549199 # Number of BP lookups
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu
|
|||
sim_ticks 26877484000 # Number of ticks simulated
|
||||
final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 175198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 176456 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51980195 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379404 # Number of bytes of host memory used
|
||||
host_seconds 517.07 # Real time elapsed on the host
|
||||
host_inst_rate 190344 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 191711 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56473959 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375760 # Number of bytes of host memory used
|
||||
host_seconds 475.93 # Real time elapsed on the host
|
||||
sim_insts 90589798 # Number of instructions simulated
|
||||
sim_ops 91240351 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1671585 # In
|
|||
system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15506 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 992384 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis
|
||||
|
|
@ -214,10 +215,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 992384 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks)
|
||||
|
|
@ -546,12 +547,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
|
|||
sim_ticks 147135976000 # Number of ticks simulated
|
||||
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 662214 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 666963 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1075722156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375060 # Number of bytes of host memory used
|
||||
host_seconds 136.78 # Real time elapsed on the host
|
||||
host_inst_rate 529408 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 533204 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 859987474 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 373720 # Number of bytes of host memory used
|
||||
host_seconds 171.09 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 792 # Tr
|
|||
system.membus.trans_dist::ReadResp 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 981760 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
|
||||
|
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 653861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 969395755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365508 # Number of bytes of host memory used
|
||||
host_seconds 372.90 # Real time elapsed on the host
|
||||
host_inst_rate 810264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 810297 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1201274596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365008 # Number of bytes of host memory used
|
||||
host_seconds 300.92 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 1036 # Tr
|
|||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 998592 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
|
|
@ -405,12 +405,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.065502 # Nu
|
|||
sim_ticks 65501881000 # Number of ticks simulated
|
||||
final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72627 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 127885 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30111215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386704 # Number of bytes of host memory used
|
||||
host_seconds 2175.33 # Real time elapsed on the host
|
||||
host_inst_rate 73961 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130234 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30664297 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 385548 # Number of bytes of host memory used
|
||||
host_seconds 2136.10 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 159263 # To
|
|||
system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 30410 # Total number of read requests seen
|
||||
system.physmem.writeReqs 163 # Total number of write requests seen
|
||||
system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 1946112 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 10432 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
|
||||
|
|
@ -232,11 +233,9 @@ system.membus.trans_dist::ReadExReq 29004 # Tr
|
|||
system.membus.trans_dist::ReadExResp 29004 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1956480 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -519,12 +518,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 466388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 821234 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1080412484 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 431468 # Number of bytes of host memory used
|
||||
host_seconds 338.75 # Real time elapsed on the host
|
||||
host_inst_rate 324809 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 571936 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 752437231 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382748 # Number of bytes of host memory used
|
||||
host_seconds 486.40 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
|
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 29024 # Tr
|
|||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1929536 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu
|
|||
sim_ticks 202349747500 # Number of ticks simulated
|
||||
final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166059 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 187221 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66507382 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250660 # Number of bytes of host memory used
|
||||
host_seconds 3042.52 # Real time elapsed on the host
|
||||
host_inst_rate 95439 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38223736 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246676 # Number of bytes of host memory used
|
||||
host_seconds 5293.82 # Real time elapsed on the host
|
||||
sim_insts 505237723 # Number of instructions simulated
|
||||
sim_ops 569624283 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 30890515 # To
|
|||
system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 148206 # Total number of read requests seen
|
||||
system.physmem.writeReqs 97667 # Total number of write requests seen
|
||||
system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 9485120 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 6250688 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis
|
||||
|
|
@ -297,10 +298,10 @@ system.membus.trans_dist::UpgradeReq 7 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101306 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101306 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15735808 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks)
|
||||
|
|
@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu
|
|||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 611042 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 688541 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 868024183 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246240 # Number of bytes of host memory used
|
||||
host_seconds 826.44 # Real time elapsed on the host
|
||||
host_inst_rate 1130634 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1274033 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1606137434 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243872 # Number of bytes of host memory used
|
||||
host_seconds 446.64 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 41855 # Tr
|
|||
system.membus.trans_dist::Writeback 95953 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15270528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
|
||||
|
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.458202 # Nu
|
|||
sim_ticks 458201684000 # Number of ticks simulated
|
||||
final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 111882 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 206882 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61997502 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341328 # Number of bytes of host memory used
|
||||
host_seconds 7390.65 # Real time elapsed on the host
|
||||
host_inst_rate 77434 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 143185 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42909026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 338808 # Number of bytes of host memory used
|
||||
host_seconds 10678.45 # Real time elapsed on the host
|
||||
sim_insts 826877109 # Number of instructions simulated
|
||||
sim_ops 1528988701 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 41005663 # To
|
|||
system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 385586 # Total number of read requests seen
|
||||
system.physmem.writeReqs 293576 # Total number of write requests seen
|
||||
system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 385586 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 293576 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 385586 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 293576 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 24677504 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 18788864 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis
|
||||
|
|
@ -316,11 +317,9 @@ system.membus.trans_dist::ReadExReq 206848 # Tr
|
|||
system.membus.trans_dist::ReadExResp 206848 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43466368 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -606,12 +605,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 146337 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7664164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7810501 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311349248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 311784960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
|
|||
sim_ticks 1647872849000 # Number of ticks simulated
|
||||
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 533286 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 986105 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1062778196 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304632 # Number of bytes of host memory used
|
||||
host_seconds 1550.53 # Real time elapsed on the host
|
||||
host_inst_rate 418246 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 773383 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 833516309 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254900 # Number of bytes of host memory used
|
||||
host_seconds 1977.01 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
|
||||
|
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 206691 # Tr
|
|||
system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43099456 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.139916 # Nu
|
|||
sim_ticks 139916242500 # Number of ticks simulated
|
||||
final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84616 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29697100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231112 # Number of bytes of host memory used
|
||||
host_seconds 4711.44 # Real time elapsed on the host
|
||||
host_inst_rate 80792 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 80792 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28354866 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231004 # Number of bytes of host memory used
|
||||
host_seconds 4934.47 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1536462 # In
|
|||
system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7328 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 468992 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
|
||||
|
|
@ -245,10 +246,10 @@ system.membus.trans_dist::ReadReq 4183 # Tr
|
|||
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 468992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks)
|
||||
|
|
@ -447,12 +448,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16759 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 557056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu
|
|||
sim_ticks 77521581000 # Number of ticks simulated
|
||||
final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 159390 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 159390 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32899346 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233160 # Number of bytes of host memory used
|
||||
host_seconds 2356.33 # Real time elapsed on the host
|
||||
host_inst_rate 226587 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 226587 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46769350 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233048 # Number of bytes of host memory used
|
||||
host_seconds 1657.53 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2850716 # In
|
|||
system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7442 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 476288 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis
|
||||
|
|
@ -242,10 +243,10 @@ system.membus.trans_dist::ReadReq 4310 # Tr
|
|||
system.membus.trans_dist::ReadResp 4310 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 476288 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks)
|
||||
|
|
@ -561,12 +562,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1715092 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2440727076 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230984 # Number of bytes of host memory used
|
||||
host_seconds 232.45 # Real time elapsed on the host
|
||||
host_inst_rate 1598767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2275187152 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229960 # Number of bytes of host memory used
|
||||
host_seconds 249.36 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4032 # Tr
|
|||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 459136 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
|
||||
|
|
@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu
|
|||
sim_ticks 68375005500 # Number of ticks simulated
|
||||
final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 171790 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 219625 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43020256 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254724 # Number of bytes of host memory used
|
||||
host_seconds 1589.37 # Real time elapsed on the host
|
||||
host_inst_rate 121198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30350947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251080 # Number of bytes of host memory used
|
||||
host_seconds 2252.81 # Real time elapsed on the host
|
||||
sim_insts 273036725 # Number of instructions simulated
|
||||
sim_ops 349064449 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 2839868 # In
|
|||
system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7288 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 466432 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis
|
||||
|
|
@ -243,10 +244,10 @@ system.membus.trans_dist::UpgradeReq 5 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2821 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2821 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 466432 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks)
|
||||
|
|
@ -575,12 +576,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu
|
|||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 442791 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 566092 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 853689730 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250392 # Number of bytes of host memory used
|
||||
host_seconds 615.96 # Real time elapsed on the host
|
||||
host_inst_rate 414348 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 529728 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 798851724 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248008 # Number of bytes of host memory used
|
||||
host_seconds 658.24 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3976 # Tr
|
|||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 437248 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
|
||||
|
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu
|
|||
sim_ticks 631883288500 # Number of ticks simulated
|
||||
final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 129491 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 129491 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44882876 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237188 # Number of bytes of host memory used
|
||||
host_seconds 14078.49 # Real time elapsed on the host
|
||||
host_inst_rate 177291 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 177291 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61450789 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236780 # Number of bytes of host memory used
|
||||
host_seconds 10282.75 # Real time elapsed on the host
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_ops 1823043370 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6776745 # To
|
|||
system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 476114 # Total number of read requests seen
|
||||
system.physmem.writeReqs 66908 # Total number of write requests seen
|
||||
system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30471232 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis
|
||||
|
|
@ -262,10 +263,10 @@ system.membus.trans_dist::ReadResp 409257 # Tr
|
|||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34753344 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks)
|
||||
|
|
@ -581,12 +582,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20089 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159776 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3179865 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 642816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 104827200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu
|
|||
sim_ticks 2769739533000 # Number of ticks simulated
|
||||
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1559352 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2149839105 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233980 # Number of bytes of host memory used
|
||||
host_seconds 1288.35 # Real time elapsed on the host
|
||||
host_inst_rate 892879 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 892879 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1230989339 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233984 # Number of bytes of host memory used
|
||||
host_seconds 2250.01 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408476 # Tr
|
|||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34704448 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
|
||||
|
|
@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu
|
|||
sim_ticks 640648369500 # Number of ticks simulated
|
||||
final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 99606 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 135651 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46095119 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254320 # Number of bytes of host memory used
|
||||
host_seconds 13898.40 # Real time elapsed on the host
|
||||
host_inst_rate 107808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49890421 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251704 # Number of bytes of host memory used
|
||||
host_seconds 12841.11 # Real time elapsed on the host
|
||||
sim_insts 1384370590 # Number of instructions simulated
|
||||
sim_ops 1885325342 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 6603111 # To
|
|||
system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 474992 # Total number of read requests seen
|
||||
system.physmem.writeReqs 66098 # Total number of write requests seen
|
||||
system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30399488 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
|
||||
|
|
@ -244,10 +245,10 @@ system.membus.trans_dist::UpgradeReq 4361 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34629696 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
|
||||
|
|
@ -576,12 +577,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
|
|||
sim_ticks 2326118592000 # Number of ticks simulated
|
||||
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 575384 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 780549 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 968736790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250996 # Number of bytes of host memory used
|
||||
host_seconds 2401.19 # Real time elapsed on the host
|
||||
host_inst_rate 481372 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653016 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 810455855 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248632 # Number of bytes of host memory used
|
||||
host_seconds 2870.14 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 408063 # Tr
|
|||
system.membus.trans_dist::Writeback 66099 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34576320 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
|
||||
|
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.043769 # Nu
|
|||
sim_ticks 43769191000 # Number of ticks simulated
|
||||
final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 112888 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 112888 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55931443 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233228 # Number of bytes of host memory used
|
||||
host_seconds 782.55 # Real time elapsed on the host
|
||||
host_inst_rate 69144 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69144 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34257993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232832 # Number of bytes of host memory used
|
||||
host_seconds 1277.63 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 166688208 # To
|
|||
system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165515 # Total number of read requests seen
|
||||
system.physmem.writeReqs 113997 # Total number of write requests seen
|
||||
system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 10592960 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis
|
||||
|
|
@ -311,10 +312,10 @@ system.membus.trans_dist::ReadResp 34625 # Tr
|
|||
system.membus.trans_dist::Writeback 113997 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17888768 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks)
|
||||
|
|
@ -513,12 +514,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu
|
|||
sim_ticks 24977022500 # Number of ticks simulated
|
||||
final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 130696 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130696 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41014411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236320 # Number of bytes of host memory used
|
||||
host_seconds 608.98 # Real time elapsed on the host
|
||||
host_inst_rate 124025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 124025 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38920856 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235900 # Number of bytes of host memory used
|
||||
host_seconds 641.74 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 292149475 # To
|
|||
system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 166305 # Total number of read requests seen
|
||||
system.physmem.writeReqs 114016 # Total number of write requests seen
|
||||
system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 10643520 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7297024 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis
|
||||
|
|
@ -309,10 +310,10 @@ system.membus.trans_dist::ReadResp 35508 # Tr
|
|||
system.membus.trans_dist::Writeback 114016 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130797 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130797 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17940544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks)
|
||||
|
|
@ -628,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
|||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 671194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 671194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1015328507 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233108 # Number of bytes of host memory used
|
||||
host_seconds 131.62 # Real time elapsed on the host
|
||||
host_inst_rate 775893 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 775893 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1173708198 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233104 # Number of bytes of host memory used
|
||||
host_seconds 113.86 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 34272 # Tr
|
|||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17864640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
|
||||
|
|
@ -427,12 +427,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu
|
|||
sim_ticks 26765004500 # Number of ticks simulated
|
||||
final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 88779 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125988 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33510752 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255124 # Number of bytes of host memory used
|
||||
host_seconds 798.70 # Real time elapsed on the host
|
||||
host_inst_rate 102307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 145187 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38617115 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251228 # Number of bytes of host memory used
|
||||
host_seconds 693.09 # Real time elapsed on the host
|
||||
sim_insts 70907629 # Number of instructions simulated
|
||||
sim_ops 100626876 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 200715827 # To
|
|||
system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 128790 # Total number of read requests seen
|
||||
system.physmem.writeReqs 83940 # Total number of write requests seen
|
||||
system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 8242496 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 5372160 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis
|
||||
|
|
@ -313,10 +314,10 @@ system.membus.trans_dist::UpgradeReq 321 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 321 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102252 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102252 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13614656 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks)
|
||||
|
|
@ -645,12 +646,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
|
|||
sim_ticks 132689045000 # Number of ticks simulated
|
||||
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 438025 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 621131 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825892843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249772 # Number of bytes of host memory used
|
||||
host_seconds 160.66 # Real time elapsed on the host
|
||||
host_inst_rate 525201 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 744748 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 990262559 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247408 # Number of bytes of host memory used
|
||||
host_seconds 133.99 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 25532 # Tr
|
|||
system.membus.trans_dist::Writeback 83909 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13550144 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
|
||||
|
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
|
|||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 840510 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1264790801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241580 # Number of bytes of host memory used
|
||||
host_seconds 159.90 # Real time elapsed on the host
|
||||
host_inst_rate 788005 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 798208 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1185781953 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240044 # Number of bytes of host memory used
|
||||
host_seconds 170.56 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 30277 # Tr
|
|||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13721664 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
|
||||
|
|
@ -415,12 +415,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.017017 # Nu
|
|||
sim_ticks 1017016979500 # Number of ticks simulated
|
||||
final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113008 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 113008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63156510 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225148 # Number of bytes of host memory used
|
||||
host_seconds 16103.12 # Real time elapsed on the host
|
||||
host_inst_rate 89946 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50268200 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224748 # Number of bytes of host memory used
|
||||
host_seconds 20231.82 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 64065511 # To
|
|||
system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959691 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 125420224 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis
|
||||
|
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1178393 # Tr
|
|||
system.membus.trans_dist::Writeback 1018058 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781298 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781298 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575936 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks)
|
||||
|
|
@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1718 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916181 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21917899 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819502720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819557696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu
|
|||
sim_ticks 694171131000 # Number of ticks simulated
|
||||
final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 169313 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 169313 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67701038 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228220 # Number of bytes of host memory used
|
||||
host_seconds 10253.48 # Real time elapsed on the host
|
||||
host_inst_rate 178600 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 178600 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 71414604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227828 # Number of bytes of host memory used
|
||||
host_seconds 9720.30 # Real time elapsed on the host
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_ops 1736043781 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 94013475 # To
|
|||
system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1966438 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1019710 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 1966438 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1019710 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 1966438 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1019710 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 125852032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65261440 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 561 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis
|
||||
|
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1191259 # Tr
|
|||
system.membus.trans_dist::Writeback 1019710 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 775179 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 775179 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4952586 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 191113472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 191113472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks)
|
||||
|
|
@ -635,12 +636,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085475 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22087401 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825936384 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 825998016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
|||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 781919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 781919 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1127211275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225028 # Number of bytes of host memory used
|
||||
host_seconds 2327.32 # Real time elapsed on the host
|
||||
host_inst_rate 1731328 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2495874089 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225024 # Number of bytes of host memory used
|
||||
host_seconds 1051.09 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1178362 # Tr
|
|||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575360 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
|
||||
|
|
@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu
|
|||
sim_ticks 541686426500 # Number of ticks simulated
|
||||
final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 161069 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 179684 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56487595 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246340 # Number of bytes of host memory used
|
||||
host_seconds 9589.48 # Real time elapsed on the host
|
||||
host_inst_rate 146656 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163606 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 51433162 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242412 # Number of bytes of host memory used
|
||||
host_seconds 10531.85 # Real time elapsed on the host
|
||||
sim_insts 1544563023 # Number of instructions simulated
|
||||
sim_ops 1723073835 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory
|
||||
|
|
@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 130020847 # To
|
|||
system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 2246464 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1100477 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 143773696 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 70430528 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis
|
||||
|
|
@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp 1420070 # Tr
|
|||
system.membus.trans_dist::Writeback 1100477 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 826393 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 826393 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 214204160 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks)
|
||||
|
|
@ -644,12 +645,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu
|
|||
sim_ticks 2391205115000 # Number of ticks simulated
|
||||
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1401168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2177389973 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243008 # Number of bytes of host memory used
|
||||
host_seconds 1098.20 # Real time elapsed on the host
|
||||
host_inst_rate 594937 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 663956 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 924522029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240640 # Number of bytes of host memory used
|
||||
host_seconds 2586.42 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
|
|
@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1177898 # Tr
|
|||
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190462208 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
|
||||
|
|
@ -445,12 +445,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
|
|||
sim_ticks 5882580526000 # Number of ticks simulated
|
||||
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 548624 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295308 # Number of bytes of host memory used
|
||||
host_seconds 5482.96 # Real time elapsed on the host
|
||||
host_inst_rate 645050 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1261455450 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245540 # Number of bytes of host memory used
|
||||
host_seconds 4663.33 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
|
|
@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 781295 # Tr
|
|||
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190549120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -396,12 +394,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.041672 # Nu
|
|||
sim_ticks 41671895000 # Number of ticks simulated
|
||||
final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84546 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84546 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38336000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228812 # Number of bytes of host memory used
|
||||
host_seconds 1087.02 # Real time elapsed on the host
|
||||
host_inst_rate 101828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46172411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228672 # Number of bytes of host memory used
|
||||
host_seconds 902.53 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 4291046 # In
|
|||
system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 4938 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 316032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis
|
||||
|
|
@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3216 # Tr
|
|||
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 316032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks)
|
||||
|
|
@ -441,12 +442,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 23593 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 758400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu
|
|||
sim_ticks 23492267500 # Number of ticks simulated
|
||||
final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 122951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 122951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34312389 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231868 # Number of bytes of host memory used
|
||||
host_seconds 684.66 # Real time elapsed on the host
|
||||
host_inst_rate 120531 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120531 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33636905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231740 # Number of bytes of host memory used
|
||||
host_seconds 698.41 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 8339084 # In
|
|||
system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5226 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 334464 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis
|
||||
|
|
@ -239,10 +240,10 @@ system.membus.trans_dist::ReadReq 3520 # Tr
|
|||
system.membus.trans_dist::ReadResp 3520 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1706 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1706 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 334464 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks)
|
||||
|
|
@ -557,12 +558,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
|||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 852211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 852211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1100968725 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2022504 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2612866318 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228676 # Number of bytes of host memory used
|
||||
host_seconds 107.84 # Real time elapsed on the host
|
||||
host_seconds 45.44 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 3043 # Tr
|
|||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 304960 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
|
|
@ -417,12 +417,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu
|
|||
sim_ticks 74201024500 # Number of ticks simulated
|
||||
final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 81530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89268 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35110326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249620 # Number of bytes of host memory used
|
||||
host_seconds 2113.37 # Real time elapsed on the host
|
||||
host_inst_rate 88798 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 97225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38240010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245976 # Number of bytes of host memory used
|
||||
host_seconds 1940.40 # Real time elapsed on the host
|
||||
sim_insts 172303021 # Number of instructions simulated
|
||||
sim_ops 188656503 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1769895 # In
|
|||
system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3801 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 243200 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis
|
||||
|
|
@ -238,10 +239,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 243200 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks)
|
||||
|
|
@ -571,12 +572,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
|
|||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1198657 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618778979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245268 # Number of bytes of host memory used
|
||||
host_seconds 143.36 # Real time elapsed on the host
|
||||
host_inst_rate 705973 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 773116 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 953412259 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242928 # Number of bytes of host memory used
|
||||
host_seconds 243.41 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 2361 # Tr
|
|||
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 220992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
|
||||
|
|
@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
|
|||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 942019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 942020 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1317563963 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238020 # Number of bytes of host memory used
|
||||
host_seconds 205.35 # Real time elapsed on the host
|
||||
host_inst_rate 872463 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 872464 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1220278409 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236504 # Number of bytes of host memory used
|
||||
host_seconds 221.72 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 4095 # Tr
|
|||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 331072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
|
||||
|
|
@ -400,12 +400,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.144471 # Nu
|
|||
sim_ticks 144470654000 # Number of ticks simulated
|
||||
final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76550 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83736451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279024 # Number of bytes of host memory used
|
||||
host_seconds 1725.30 # Real time elapsed on the host
|
||||
host_inst_rate 75912 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 127236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83039301 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277792 # Number of bytes of host memory used
|
||||
host_seconds 1739.79 # Real time elapsed on the host
|
||||
sim_insts 132071192 # Number of instructions simulated
|
||||
sim_ops 221362962 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1500429 # In
|
|||
system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5340 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 341760 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis
|
||||
|
|
@ -242,11 +243,9 @@ system.membus.trans_dist::ReadExReq 1530 # Tr
|
|||
system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 341696 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -531,12 +530,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
|||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 679792 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1139391 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1291700674 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272716 # Number of bytes of host memory used
|
||||
host_seconds 194.28 # Real time elapsed on the host
|
||||
host_inst_rate 352771 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 591275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 670313887 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270496 # Number of bytes of host memory used
|
||||
host_seconds 374.38 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221362963 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
|
||||
|
|
@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 1575 # Tr
|
|||
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 303040 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -389,12 +387,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1416644 # To
|
|||
system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
|||
|
|
@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 469015 # To
|
|||
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.961841 # Nu
|
|||
sim_ticks 1961841175000 # Number of ticks simulated
|
||||
final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1094895 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36191186298 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308248 # Number of bytes of host memory used
|
||||
host_seconds 54.21 # Real time elapsed on the host
|
||||
host_inst_rate 1272238 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42053157352 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308880 # Number of bytes of host memory used
|
||||
host_seconds 46.65 # Real time elapsed on the host
|
||||
sim_insts 59351715 # Number of instructions simulated
|
||||
sim_ops 59351715 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory
|
||||
|
|
@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1351188 # To
|
|||
system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 448702 # Total number of read requests seen
|
||||
system.physmem.writeReqs 121037 # Total number of write requests seen
|
||||
system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28716928 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7746368 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis
|
||||
|
|
@ -332,16 +333,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644
|
|||
system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 36531890 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
|
||||
|
|
@ -941,16 +938,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 894 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 205232754 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks)
|
||||
|
|
@ -985,19 +982,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -1014,19 +998,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2730242 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.918473 # Nu
|
|||
sim_ticks 1918473094000 # Number of ticks simulated
|
||||
final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 813863 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 813863 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27788392408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306196 # Number of bytes of host memory used
|
||||
host_seconds 69.04 # Real time elapsed on the host
|
||||
host_inst_rate 948634 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 948634 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32389976926 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304780 # Number of bytes of host memory used
|
||||
host_seconds 59.23 # Real time elapsed on the host
|
||||
sim_insts 56188014 # Number of instructions simulated
|
||||
sim_ops 56188014 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory
|
||||
|
|
@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 443419 # To
|
|||
system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 442977 # Total number of read requests seen
|
||||
system.physmem.writeReqs 115467 # Total number of write requests seen
|
||||
system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28350528 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7389888 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis
|
||||
|
|
@ -329,16 +330,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 8
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 35784972 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
|
||||
|
|
@ -644,19 +641,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -673,19 +657,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio
|
|||
system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 2706164 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
|
|
@ -1112,12 +1083,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -66,14 +66,15 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To
|
|||
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
|||
|
|
@ -49,14 +49,15 @@ system.physmem.bw_total::cpu.itb.walker 82 # To
|
|||
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 662335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 851722 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25577480180 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 396424 # Number of bytes of host memory used
|
||||
host_seconds 91.21 # Real time elapsed on the host
|
||||
host_inst_rate 691261 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 888919 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26694508777 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 395580 # Number of bytes of host memory used
|
||||
host_seconds 87.39 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
|
@ -62,14 +62,15 @@ system.physmem.bw_total::cpu0.data 3386724 # To
|
|||
system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
@ -450,10 +451,10 @@ system.cpu0.num_fp_register_writes 1428 # nu
|
|||
system.cpu0.num_mem_refs 15013057 # number of memory refs
|
||||
system.cpu0.num_load_insts 8304661 # Number of load instructions
|
||||
system.cpu0.num_store_insts 6708396 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
|
||||
system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 850590 # number of replacements
|
||||
|
|
@ -660,10 +661,10 @@ system.cpu1.num_fp_register_writes 1352 # nu
|
|||
system.cpu1.num_mem_refs 12348580 # number of memory refs
|
||||
system.cpu1.num_load_insts 7334866 # Number of load instructions
|
||||
system.cpu1.num_store_insts 5013714 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles
|
||||
system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112102 # Nu
|
|||
sim_ticks 5112102211000 # Number of ticks simulated
|
||||
final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 878832 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22473674513 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586256 # Number of bytes of host memory used
|
||||
host_seconds 227.47 # Real time elapsed on the host
|
||||
host_inst_rate 856407 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 584104 # Number of bytes of host memory used
|
||||
host_seconds 233.43 # Real time elapsed on the host
|
||||
sim_insts 199908396 # Number of instructions simulated
|
||||
sim_ops 409304707 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
|
||||
|
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 63 # To
|
|||
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 0 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 0 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.196173 # Nu
|
|||
sim_ticks 5196173457000 # Number of ticks simulated
|
||||
final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 766970 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31067837744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 586132 # Number of bytes of host memory used
|
||||
host_seconds 167.25 # Real time elapsed on the host
|
||||
host_inst_rate 457062 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 881101 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18514311716 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 585140 # Number of bytes of host memory used
|
||||
host_seconds 280.66 # Real time elapsed on the host
|
||||
sim_insts 128277551 # Number of instructions simulated
|
||||
sim_ops 247287193 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory
|
||||
|
|
@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To
|
|||
system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 198391 # Total number of read requests seen
|
||||
system.physmem.writeReqs 126842 # Total number of write requests seen
|
||||
system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 198391 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 126842 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 198391 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 126842 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 12697024 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 8117888 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis
|
||||
|
|
@ -358,39 +359,31 @@ system.membus.trans_dist::MessageReq 1655 # Tr
|
|||
system.membus.trans_dist::MessageResp 1655 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22488073 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 256571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 359320500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.occupancy 1351024000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -532,26 +525,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side
|
|||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -576,26 +549,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid
|
|||
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.data_through_bus 3280192 # Total data (bytes)
|
||||
system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks)
|
||||
|
|
@ -1032,16 +985,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # T
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 25046000 # Number of ticks simulated
|
||||
final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25238 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98905790 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225424 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 22373 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22372 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 87684145 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225308 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 766589475 # In
|
|||
system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 29952 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
|
||||
|
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 396 # Tr
|
|||
system.membus.trans_dist::ReadResp 395 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29952 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
|
||||
|
|
@ -396,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20671000 # Number of ticks simulated
|
||||
final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25591 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25589 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 83008053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227468 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 24570 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24568 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 79697022 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227340 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 969087127 # In
|
|||
system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 488 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 31168 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
|
||||
|
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 415 # Tr
|
|||
system.membus.trans_dist::ReadResp 414 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 31168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks)
|
||||
|
|
@ -511,12 +512,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 416 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101141711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224276 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
host_inst_rate 27670 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27667 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 140894748 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224272 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 373 # Tr
|
|||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
|
||||
|
|
@ -403,12 +403,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 374 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 11933500 # Number of ticks simulated
|
||||
final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2461163 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226156 # Number of bytes of host memory used
|
||||
host_seconds 4.85 # Real time elapsed on the host
|
||||
host_inst_rate 64 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 321705 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226036 # Number of bytes of host memory used
|
||||
host_seconds 37.09 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1008254075 # In
|
|||
system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 273 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 17472 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
|
||||
|
|
@ -190,10 +191,10 @@ system.membus.trans_dist::ReadReq 249 # Tr
|
|||
system.membus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17472 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
|
||||
|
|
@ -507,12 +508,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 249 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 376 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 546 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 16524000 # Number of ticks simulated
|
||||
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 252355 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 251860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1611932908 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223992 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 70 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 70 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 446596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222964 # Number of bytes of host memory used
|
||||
host_seconds 37.00 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 218 # Tr
|
|||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15680 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
|
||||
|
|
@ -397,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 218 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu
|
|||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31208 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 112083077 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 32065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 40006 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 115159682 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240696 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In
|
|||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 25152 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
|
||||
|
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr
|
|||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
|
|
@ -563,12 +564,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu
|
|||
sim_ticks 16494000 # Number of ticks simulated
|
||||
final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 66928 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 240363471 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244336 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 36590 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45651 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 131406771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240696 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1051533891 # In
|
|||
system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 393 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 25152 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
|
||||
|
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 352 # Tr
|
|||
system.membus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 25152 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks)
|
||||
|
|
@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 397 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu
|
|||
sim_ticks 25969000 # Number of ticks simulated
|
||||
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 220478 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 273604 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1251201624 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241012 # Number of bytes of host memory used
|
||||
host_inst_rate 229244 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 284503 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1301168988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238660 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4565 # Number of instructions simulated
|
||||
sim_ops 5672 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 307 # Tr
|
|||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22400 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
|
||||
|
|
@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 339 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 24587000 # Number of ticks simulated
|
||||
final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 41260 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41253 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174426700 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226212 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 52979 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52966 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 223940501 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224928 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 825151503 # In
|
|||
system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 455 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 29120 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 404 # Tr
|
|||
system.membus.trans_dist::ReadResp 404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 29120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks)
|
||||
|
|
@ -382,12 +383,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 21805500 # Number of ticks simulated
|
||||
final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79844 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 337538221 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228256 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 44396 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44386 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 187676879 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228012 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 983238174 # In
|
|||
system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 477 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30528 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
|
||||
|
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 426 # Tr
|
|||
system.membus.trans_dist::ReadResp 426 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
|
||||
|
|
@ -495,12 +496,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 429 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu
|
|||
sim_ticks 31633000 # Number of ticks simulated
|
||||
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 482351 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 481309 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2613274672 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225064 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 304637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 304230 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1653175117 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224940 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 388 # Tr
|
|||
system.membus.trans_dist::ReadResp 388 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28096 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
|
||||
|
|
@ -389,12 +389,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 390 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu
|
|||
sim_ticks 18469500 # Number of ticks simulated
|
||||
final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 54927 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 54916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 175080000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224296 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 100626 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 320728752 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223260 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1195484447 # In
|
|||
system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 446 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 28544 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
|
||||
|
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 399 # Tr
|
|||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks)
|
||||
|
|
@ -493,12 +494,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 406 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20802500 # Number of ticks simulated
|
||||
final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 39959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39952 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155990706 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232536 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_inst_rate 86492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 86452 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 337526822 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231936 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 889123903 # In
|
|||
system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 423 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 27072 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis
|
||||
|
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 342 # Tr
|
|||
system.membus.trans_dist::ReadResp 342 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
|
||||
|
|
@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 345 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 27800000 # Number of ticks simulated
|
||||
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 413138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 412367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2148212772 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231400 # Number of bytes of host memory used
|
||||
host_inst_rate 441877 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 441389 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2300957264 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230904 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 308 # Tr
|
|||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 24896 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
|
||||
|
|
@ -374,12 +374,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 311 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 19639500 # Number of ticks simulated
|
||||
final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 28578 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51768 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 104294046 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245432 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_inst_rate 30549 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55338 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 111488682 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243516 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 892894422 # In
|
|||
system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 417 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 26624 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
|
||||
|
|
@ -195,11 +196,9 @@ system.membus.trans_dist::ReadExReq 77 # Tr
|
|||
system.membus.trans_dist::ReadExResp 77 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 26624 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -478,12 +477,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 342 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 28358000 # Number of ticks simulated
|
||||
final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 90736 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 477859669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289160 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 186481 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 337520 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 981039317 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241472 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
|
||||
|
|
@ -34,11 +34,9 @@ system.membus.trans_dist::ReadExReq 79 # Tr
|
|||
system.membus.trans_dist::ReadExResp 79 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 23104 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
|
|
@ -375,12 +373,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 283 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 24404000 # Number of ticks simulated
|
||||
final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52847 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52845 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101181200 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228064 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 780 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 780 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1494307 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227936 # Number of bytes of host memory used
|
||||
host_seconds 16.33 # Real time elapsed on the host
|
||||
sim_insts 12745 # Number of instructions simulated
|
||||
sim_ops 12745 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1636453040 # In
|
|||
system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 974 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 62336 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis
|
||||
|
|
@ -205,10 +206,10 @@ system.membus.trans_dist::ReadReq 828 # Tr
|
|||
system.membus.trans_dist::ReadResp 828 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 62336 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks)
|
||||
|
|
@ -452,41 +453,7 @@ system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_1::total 10798 # Type of FU issued
|
||||
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued
|
||||
system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued
|
||||
system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type::total 21796 # Type of FU issued
|
||||
system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.rate 0.446557 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested
|
||||
|
|
@ -662,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 830 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
|||
sim_ticks 27282000 # Number of ticks simulated
|
||||
final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50184 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 50180 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 90285398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232468 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_inst_rate 96636 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 96628 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 173854426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231852 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 699068983 # In
|
|||
system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 436 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 27904 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis
|
||||
|
|
@ -195,10 +196,10 @@ system.membus.trans_dist::ReadReq 351 # Tr
|
|||
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 27840 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
|
||||
|
|
@ -364,12 +365,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 354 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
|||
sim_ticks 26524500 # Number of ticks simulated
|
||||
final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52709 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 96835127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234512 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_inst_rate 95044 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 174603061 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232868 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
|
||||
|
|
@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 808309299 # In
|
|||
system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 482 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 30848 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
|
||||
|
|
@ -194,10 +195,10 @@ system.membus.trans_dist::ReadReq 399 # Tr
|
|||
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 30848 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
|
||||
|
|
@ -472,12 +473,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 401 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 968 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 30976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu
|
|||
sim_ticks 41368000 # Number of ticks simulated
|
||||
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 479032 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231320 # Number of bytes of host memory used
|
||||
host_inst_rate 554996 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 554737 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1512828488 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230824 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 331 # Tr
|
|||
system.membus.trans_dist::ReadResp 331 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 26624 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
|
||||
|
|
@ -375,12 +375,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 333 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu
|
|||
sim_ticks 110804500 # Number of ticks simulated
|
||||
final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 110530 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11745373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249508 # Number of bytes of host memory used
|
||||
host_seconds 9.43 # Real time elapsed on the host
|
||||
host_inst_rate 170931 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 170931 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18163832 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247816 # Number of bytes of host memory used
|
||||
host_seconds 6.10 # Real time elapsed on the host
|
||||
sim_insts 1042724 # Number of instructions simulated
|
||||
sim_ops 1042724 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
|
||||
|
|
@ -57,14 +57,15 @@ system.physmem.bw_total::cpu2.data 11551877 # To
|
|||
system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 660 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 42176 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
|
||||
|
|
@ -229,16 +230,421 @@ system.membus.trans_dist::UpgradeReq 287 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 163 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 42176 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 11 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 421 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
||||
system.l2c.overall_hits::total 1443 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 13 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.data 20 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
||||
system.l2c.overall_misses::total 674 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses
|
||||
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|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
||||
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|
||||
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses
|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
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|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency
|
||||
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|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.toL2Bus.throughput 1691772446 # Throughput (bytes/s)
|
||||
system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
|
||||
|
|
@ -247,24 +653,24 @@ system.toL2Bus.trans_dist::UpgradeReq 290 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 135488 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks)
|
||||
|
|
@ -2185,410 +2591,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440
|
|||
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 11 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 421 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
||||
system.l2c.overall_hits::total 1443 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 13 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.data 20 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
||||
system.l2c.overall_misses::total 674 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu
|
|||
sim_ticks 262794500 # Number of ticks simulated
|
||||
final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 146225 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146224 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57909206 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244388 # Number of bytes of host memory used
|
||||
host_seconds 4.54 # Real time elapsed on the host
|
||||
host_inst_rate 681070 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 681053 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 269712940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243700 # Number of bytes of host memory used
|
||||
host_seconds 0.97 # Real time elapsed on the host
|
||||
sim_insts 663567 # Number of instructions simulated
|
||||
sim_ops 663567 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
|
||||
|
|
@ -64,16 +64,424 @@ system.membus.trans_dist::UpgradeReq 272 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 36608 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::total 1220 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 592 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 66 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 23 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
|
||||
system.l2c.overall_misses::cpu2.data 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
|
||||
system.l2c.overall_misses::cpu3.data 16 # number of overall misses
|
||||
system.l2c.overall_misses::total 592 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.toL2Bus.throughput 646588875 # Throughput (bytes/s)
|
||||
system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
|
||||
|
|
@ -82,24 +490,24 @@ system.toL2Bus.trans_dist::UpgradeReq 274 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 23488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 116032 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks)
|
||||
|
|
@ -995,413 +1403,5 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528
|
|||
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 349.046072 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 300 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 354 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
|
||||
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
||||
system.l2c.overall_hits::total 1220 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 450 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000653 # Nu
|
|||
sim_ticks 652606500 # Number of ticks simulated
|
||||
final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 176079756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355636 # Number of bytes of host memory used
|
||||
host_seconds 3.71 # Real time elapsed on the host
|
||||
host_tick_rate 158104978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355504 # Number of bytes of host memory used
|
||||
host_seconds 4.13 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory
|
||||
|
|
@ -84,10 +84,10 @@ system.membus.trans_dist::UpgradeReq 57414 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 48586 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3092 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1086481 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks)
|
||||
|
|
@ -690,24 +690,24 @@ system.toL2Bus.trans_dist::UpgradeReq 28719 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.data_through_bus 13912273 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes)
|
||||
system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 29067628326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231288 # Number of bytes of host memory used
|
||||
host_seconds 3.44 # Real time elapsed on the host
|
||||
host_tick_rate 12102739985 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228608 # Number of bytes of host memory used
|
||||
host_seconds 8.26 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
|
||||
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
|
||||
|
|
@ -15,14 +15,15 @@ system.physmem.bw_read::cpu 2133311360 # To
|
|||
system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3333300 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller
|
||||
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
|
||||
system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
||||
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
||||
system.physmem.bytesRead 213331136 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
|
||||
|
|
@ -169,18 +170,15 @@ system.physmem.avgGap 30000.29 # Av
|
|||
system.membus.throughput 2133311360 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
|
||||
system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 213331136 # Total data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
|
||||
system.cpu.numPackets 3333300 # Number of packets generated
|
||||
system.cpu.numRetries 0 # Number of retries
|
||||
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
|
||||
system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
|
||||
|
|
@ -519,5 +517,8 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi
|
|||
system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.cpu.numPackets 3333300 # Number of packets generated
|
||||
system.cpu.numRetries 0 # Number of retries
|
||||
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 14083896029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231304 # Number of bytes of host memory used
|
||||
host_seconds 7.10 # Real time elapsed on the host
|
||||
host_tick_rate 8032030639 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228596 # Number of bytes of host memory used
|
||||
host_seconds 12.45 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
|
||||
|
|
@ -26,18 +26,15 @@ system.membus.trans_dist::ReadReq 1 # Tr
|
|||
system.membus.trans_dist::ReadResp 1 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
|
||||
system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 213329216 # Total data (bytes)
|
||||
system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
|
||||
system.cpu.numPackets 3333269 # Number of packets generated
|
||||
system.cpu.numRetries 1 # Number of retries
|
||||
system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
|
||||
system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
|
||||
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
|
||||
|
|
@ -376,5 +373,8 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% #
|
|||
system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
|
||||
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
|
||||
system.cpu.numPackets 3333269 # Number of packets generated
|
||||
system.cpu.numRetries 1 # Number of retries
|
||||
system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue