Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
This commit is contained in:
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3304da9270
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@ -53,11 +53,11 @@ int maxThreadsPerCPU = 1;
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#ifdef FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), cycleTime(p->cycleTime), checkInterrupts(true),
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: SimObject(p->name), clock(p->clock), checkInterrupts(true),
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params(p), number_of_threads(p->numberOfThreads), system(p->system)
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#else
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), cycleTime(p->cycleTime), params(p),
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: SimObject(p->name), clock(p->clock), params(p),
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number_of_threads(p->numberOfThreads)
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#endif
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{
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@ -48,12 +48,12 @@ class BaseCPU : public SimObject
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{
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protected:
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// CPU's clock period in terms of the number of ticks of curTime.
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Tick cycleTime;
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Tick clock;
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public:
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inline Tick frequency() const { return Clock::Frequency / cycleTime; }
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inline Tick cycles(int numCycles) const { return cycleTime * numCycles; }
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inline Tick curCycle() const { return curTick / cycleTime; }
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick cycles(int numCycles) const { return clock * numCycles; }
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inline Tick curCycle() const { return curTick / clock; }
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#ifdef FULL_SYSTEM
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protected:
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@ -106,7 +106,7 @@ class BaseCPU : public SimObject
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Counter max_insts_all_threads;
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Counter max_loads_any_thread;
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Counter max_loads_all_threads;
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Tick cycleTime;
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Tick clock;
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bool functionTrace;
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Tick functionTraceStart;
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#ifdef FULL_SYSTEM
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@ -71,7 +71,7 @@ class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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Param<int> cycle_time;
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Param<int> clock;
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Param<int> numThreads;
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#ifdef FULL_SYSTEM
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@ -164,7 +164,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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INIT_PARAM(cycle_time, "cpu cycle time"),
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(numThreads, "number of HW thread contexts"),
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#ifdef FULL_SYSTEM
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@ -298,7 +298,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
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AlphaSimpleParams params;
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params.cycleTime = cycle_time;
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params.clock = clock;
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params.name = getInstanceName();
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params.numberOfThreads = actual_num_threads;
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@ -831,7 +831,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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Param<int> cycle_time;
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Param<int> clock;
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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@ -863,7 +863,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
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INIT_PARAM(workload, "processes to run"),
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#endif // FULL_SYSTEM
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INIT_PARAM(cycle_time, "cpu cycle time"),
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(icache, "L1 instruction cache object"),
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INIT_PARAM(dcache, "L1 data cache object"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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@ -889,7 +889,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
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params->max_loads_any_thread = max_loads_any_thread;
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params->max_loads_all_threads = max_loads_all_threads;
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params->deferRegistration = defer_registration;
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params->cycleTime = cycle_time;
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params->clock = clock;
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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params->icache_interface = (icache) ? icache->getInterface() : NULL;
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@ -99,7 +99,7 @@ IdeController::IdeController(Params *p)
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params()->host_bus,
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params()->host_bus, 1,
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true);
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pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
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pioLatency = params()->pio_latency * params()->host_bus->clockRate;
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}
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// setup the disks attached to controller
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@ -94,7 +94,7 @@ NSGigE::NSGigE(Params *p)
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: PciDev(p), ioEnable(false),
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txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
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txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txXferLen(0), rxXferLen(0), cycleTime(p->cycle_time),
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txXferLen(0), rxXferLen(0), clock(p->clock),
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txState(txIdle), txEnable(false), CTDD(false),
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txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
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rxEnable(false), CRDD(false), rxPktBytes(0),
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@ -115,7 +115,7 @@ NSGigE::NSGigE(Params *p)
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p->header_bus, this,
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&NSGigE::cacheAccess);
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pioLatency = p->pio_latency * p->header_bus->clockRatio;
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pioLatency = p->pio_latency * p->header_bus->clockRate;
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if (p->payload_bus)
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dmaInterface = new DMAInterface<Bus>(name() + ".dma",
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@ -132,7 +132,7 @@ NSGigE::NSGigE(Params *p)
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p->payload_bus, this,
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&NSGigE::cacheAccess);
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pioLatency = p->pio_latency * p->payload_bus->clockRatio;
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pioLatency = p->pio_latency * p->payload_bus->clockRate;
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dmaInterface = new DMAInterface<Bus>(name() + ".dma",
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p->payload_bus,
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@ -2689,7 +2689,7 @@ REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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Param<Addr> addr;
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Param<Tick> cycle_time;
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Param<Tick> clock;
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Param<Tick> tx_delay;
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Param<Tick> rx_delay;
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Param<Tick> intr_delay;
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@ -2723,7 +2723,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(cycle_time, "State machine processor frequency"),
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INIT_PARAM(clock, "State machine processor frequency"),
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INIT_PARAM(tx_delay, "Transmit Delay"),
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INIT_PARAM(rx_delay, "Receive Delay"),
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INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
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@ -2769,7 +2769,7 @@ CREATE_SIM_OBJECT(NSGigE)
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params->deviceNum = pci_dev;
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params->functionNum = pci_func;
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params->cycle_time = cycle_time;
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params->clock = clock;
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params->intr_delay = intr_delay;
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params->pmem = physmem;
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params->tx_delay = tx_delay;
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@ -176,8 +176,8 @@ class NSGigE : public PciDev
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ns_desc rxDescCache;
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/* state machine cycle time */
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Tick cycleTime;
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inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
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Tick clock;
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inline Tick cycles(int numCycles) const { return numCycles * clock; }
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/* tx State Machine */
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TxState txState;
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@ -328,7 +328,7 @@ class NSGigE : public PciDev
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HierParams *hier;
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Bus *header_bus;
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Bus *payload_bus;
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Tick cycle_time;
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Tick clock;
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Tick intr_delay;
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Tick tx_delay;
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Tick rx_delay;
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@ -59,7 +59,7 @@ PciConfigAll::PciConfigAll(const string &name,
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pioInterface = newPioInterface(name, hier, bus, this,
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&PciConfigAll::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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pioLatency = pio_latency * bus->clockRate;
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}
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// Make all the pointers to devices null
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@ -98,7 +98,7 @@ Device::Device(Params *p)
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pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this,
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&Device::cacheAccess);
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pioLatency = p->pio_latency * p->io_bus->clockRatio;
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pioLatency = p->pio_latency * p->io_bus->clockRate;
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if (p->payload_bus)
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dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
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@ -112,7 +112,7 @@ Device::Device(Params *p)
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pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
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&Device::cacheAccess);
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pioLatency = p->pio_latency * p->payload_bus->clockRatio;
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pioLatency = p->pio_latency * p->payload_bus->clockRate;
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dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
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p->payload_bus, 1,
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@ -59,7 +59,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiCChip::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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pioLatency = pio_latency * bus->clockRate;
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}
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drir = 0;
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@ -175,7 +175,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiIO::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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pioLatency = pio_latency * bus->clockRate;
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}
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// set the back pointer from tsunami to myself
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@ -65,7 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiPChip::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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pioLatency = pio_latency * bus->clockRate;
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}
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@ -109,7 +109,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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pioInterface = newPioInterface(name, hier, bus, this,
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&Uart::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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pioLatency = pio_latency * bus->clockRate;
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}
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readAddr = 0;
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@ -1096,12 +1096,20 @@ def tick_check(float_ticks):
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err = (float_ticks - int_ticks) / float_ticks
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if err > frequency_tolerance:
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print >> sys.stderr, "Warning: rounding error > tolerance"
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print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks)
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#raise ValueError
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return int_ticks
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# superclass for "numeric" parameter values, to emulate math
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# operations in a type-safe way. e.g., a Latency times an int returns
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# a new Latency object.
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class NumericParamValue(ParamValue):
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def __str__(self):
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return str(self.value)
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def __float__(self):
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return float(self.value)
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def __mul__(self, other):
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newobj = self.__class__(self)
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newobj.value *= other
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@ -1109,27 +1117,31 @@ class NumericParamValue(ParamValue):
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__rmul__ = __mul__
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class Latency(NumericParamValue):
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def __init__(self, value):
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if isinstance(value, Latency):
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self.value = value.value
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elif isinstance(value, Frequency):
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self.value = 1 / value.value
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def __div__(self, other):
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newobj = self.__class__(self)
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newobj.value /= other
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return newobj
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def getLatency(value):
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if isinstance(value, Latency) or isinstance(value, Clock):
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return value.value
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elif isinstance(value, Frequency) or isinstance(value, RootClock):
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return 1 / value.value
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elif isinstance(value, str):
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try:
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self.value = toLatency(value)
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return toLatency(value)
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except ValueError:
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try:
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freq = toFrequency(value)
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return 1 / toFrequency(value)
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except ValueError:
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raise ValueError, "Latency value '%s' is neither " \
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"frequency nor period" % value
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self.value = 1 / freq
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elif value == 0:
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# the one unitless value that's OK...
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self.value = value
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else:
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raise ValueError, "Invalid Latency value '%s'" % value
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pass # fall through
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raise ValueError, "Invalid Frequency/Latency value '%s'" % value
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class Latency(NumericParamValue):
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def __init__(self, value):
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self.value = getLatency(value)
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def __getattr__(self, attr):
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if attr in ('latency', 'period'):
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@ -1138,31 +1150,13 @@ class Latency(NumericParamValue):
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return Frequency(self)
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raise AttributeError, "Latency object has no attribute '%s'" % attr
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def __str__(self):
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return str(self.value)
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# convert latency to ticks
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def ini_str(self):
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return str(tick_check(self.value * ticks_per_sec))
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class Frequency(NumericParamValue):
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def __init__(self, value):
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if isinstance(value, Frequency):
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self.value = value.value
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elif isinstance(value, Latency):
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self.value = 1 / value.value
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elif isinstance(value, str):
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try:
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self.value = toFrequency(value)
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except ValueError:
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try:
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freq = toLatency(value)
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except ValueError:
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raise ValueError, "Frequency value '%s' is neither " \
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"frequency nor period" % value
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self.value = 1 / freq
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else:
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raise ValueError, "Invalid Frequency value '%s'" % value
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self.value = 1 / getLatency(value)
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def __getattr__(self, attr):
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if attr == 'frequency':
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@ -1171,21 +1165,44 @@ class Frequency(NumericParamValue):
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return Latency(self)
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raise AttributeError, "Frequency object has no attribute '%s'" % attr
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def __str__(self):
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return str(self.value)
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def __float__(self):
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return float(self.value)
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# convert frequency to ticks per period
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def ini_str(self):
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return self.period.ini_str()
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# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz)
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class RootFrequency(Frequency):
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# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
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# We can't inherit from Frequency because we don't want it to be directly
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# assignable to a regular Frequency parameter.
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class RootClock(ParamValue):
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def __init__(self, value):
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self.value = 1 / getLatency(value)
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def __getattr__(self, attr):
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if attr == 'frequency':
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return Frequency(self)
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if attr in ('latency', 'period'):
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return Latency(self)
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raise AttributeError, "Frequency object has no attribute '%s'" % attr
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def ini_str(self):
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return str(tick_check(self.value))
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# A generic frequency and/or Latency value. Value is stored as a latency,
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# but to avoid ambiguity this object does not support numeric ops (* or /).
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# An explicit conversion to a Latency or Frequency must be made first.
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class Clock(ParamValue):
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def __init__(self, value):
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self.value = getLatency(value)
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def __getattr__(self, attr):
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if attr == 'frequency':
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return Frequency(self)
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if attr in ('latency', 'period'):
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return Latency(self)
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raise AttributeError, "Frequency object has no attribute '%s'" % attr
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def ini_str(self):
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return self.period.ini_str()
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class NetworkBandwidth(float,ParamValue):
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def __new__(cls, value):
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val = toNetworkBandwidth(value) / 8.0
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@ -1223,7 +1240,7 @@ AllMemory = AddrRange(0, MaxAddr)
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# script once config is built.
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def instantiate(root):
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global ticks_per_sec
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ticks_per_sec = float(root.frequency)
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ticks_per_sec = float(root.clock.frequency)
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root.print_ini()
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noDot = True # temporary until we fix dot
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if not noDot:
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@ -1246,7 +1263,7 @@ __all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
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'Int32', 'UInt32', 'Int64', 'UInt64',
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'Counter', 'Addr', 'Tick', 'Percent',
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'TcpPort', 'UdpPort', 'EthernetAddr',
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||||
'MemorySize', 'Latency', 'Frequency', 'RootFrequency',
|
||||
'MemorySize', 'Latency', 'Frequency', 'RootClock', 'Clock',
|
||||
'NetworkBandwidth', 'MemoryBandwidth',
|
||||
'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
|
||||
'Null', 'NULL',
|
||||
|
|
|
@ -25,4 +25,4 @@ class BaseCPU(SimObject):
|
|||
defer_registration = Param.Bool(False,
|
||||
"defer registration with system (for sampling)")
|
||||
|
||||
cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
|
||||
clock = Param.Clock(Parent.clock, "clock speed")
|
||||
|
|
|
@ -11,7 +11,7 @@ class BaseCache(BaseMem):
|
|||
block_size = Param.Int("block size in bytes")
|
||||
compressed_bus = Param.Bool(False,
|
||||
"This cache connects to a compressed memory")
|
||||
compression_latency = Param.Latency(0,
|
||||
compression_latency = Param.Latency('0ns',
|
||||
"Latency in cycles of compression algorithm")
|
||||
do_copy = Param.Bool(False, "perform fast copies in the cache")
|
||||
hash_delay = Param.Int(1, "time in cycles of hash access")
|
||||
|
|
|
@ -2,7 +2,7 @@ from m5 import *
|
|||
class BaseSystem(SimObject):
|
||||
type = 'BaseSystem'
|
||||
abstract = True
|
||||
boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
|
||||
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
|
||||
"boot processor frequency")
|
||||
memctrl = Param.MemoryController(Parent.any, "memory controller")
|
||||
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
|
||||
|
|
|
@ -3,5 +3,5 @@ from BaseHier import BaseHier
|
|||
|
||||
class Bus(BaseHier):
|
||||
type = 'Bus'
|
||||
clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
|
||||
clock = Param.Clock("bus frequency")
|
||||
width = Param.Int("bus width in bytes")
|
||||
|
|
|
@ -58,7 +58,7 @@ class NSGigE(PciDevice):
|
|||
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
||||
"Ethernet Hardware Address")
|
||||
|
||||
cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
|
||||
clock = Param.Clock('100MHz', "State machine processor frequency")
|
||||
|
||||
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
||||
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
||||
|
@ -95,7 +95,7 @@ class Sinic(PciDevice):
|
|||
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
||||
"Ethernet Hardware Address")
|
||||
|
||||
cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
|
||||
clock = Param.Clock('100MHz', "State machine processor frequency")
|
||||
|
||||
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
||||
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
||||
|
|
|
@ -6,7 +6,7 @@ from Trace import Trace
|
|||
|
||||
class Root(SimObject):
|
||||
type = 'Root'
|
||||
frequency = Param.RootFrequency('200MHz', "tick frequency")
|
||||
clock = Param.RootClock('200MHz', "tick frequency")
|
||||
output_file = Param.String('cout', "file to dump simulator output to")
|
||||
checkpoint = Param.String('', "checkpoint file to load")
|
||||
# hier = Param.HierParams(HierParams(do_data = False, do_events = True),
|
||||
|
|
|
@ -85,14 +85,14 @@ class Root : public SimObject
|
|||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
|
||||
|
||||
Param<Tick> frequency;
|
||||
Param<Tick> clock;
|
||||
Param<string> output_file;
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(Root)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
|
||||
|
||||
INIT_PARAM(frequency, "tick frequency"),
|
||||
INIT_PARAM(clock, "tick frequency"),
|
||||
INIT_PARAM(output_file, "file to dump simulator output to")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(Root)
|
||||
|
@ -109,7 +109,7 @@ CREATE_SIM_OBJECT(Root)
|
|||
Root *root = new Root(getInstanceName());
|
||||
|
||||
using namespace Clock;
|
||||
Frequency = frequency;
|
||||
Frequency = clock;
|
||||
Float::s = static_cast<double>(Frequency);
|
||||
Float::ms = Float::s / 1.0e3;
|
||||
Float::us = Float::s / 1.0e6;
|
||||
|
|
Loading…
Reference in a new issue