diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 1077c8a51..fd91749f7 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -53,11 +53,11 @@ int maxThreadsPerCPU = 1; #ifdef FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : SimObject(p->name), cycleTime(p->cycleTime), checkInterrupts(true), + : SimObject(p->name), clock(p->clock), checkInterrupts(true), params(p), number_of_threads(p->numberOfThreads), system(p->system) #else BaseCPU::BaseCPU(Params *p) - : SimObject(p->name), cycleTime(p->cycleTime), params(p), + : SimObject(p->name), clock(p->clock), params(p), number_of_threads(p->numberOfThreads) #endif { diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index ea12460db..f38a6c939 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -48,12 +48,12 @@ class BaseCPU : public SimObject { protected: // CPU's clock period in terms of the number of ticks of curTime. - Tick cycleTime; + Tick clock; public: - inline Tick frequency() const { return Clock::Frequency / cycleTime; } - inline Tick cycles(int numCycles) const { return cycleTime * numCycles; } - inline Tick curCycle() const { return curTick / cycleTime; } + inline Tick frequency() const { return Clock::Frequency / clock; } + inline Tick cycles(int numCycles) const { return clock * numCycles; } + inline Tick curCycle() const { return curTick / clock; } #ifdef FULL_SYSTEM protected: @@ -106,7 +106,7 @@ class BaseCPU : public SimObject Counter max_insts_all_threads; Counter max_loads_any_thread; Counter max_loads_all_threads; - Tick cycleTime; + Tick clock; bool functionTrace; Tick functionTraceStart; #ifdef FULL_SYSTEM diff --git a/cpu/beta_cpu/alpha_full_cpu_builder.cc b/cpu/beta_cpu/alpha_full_cpu_builder.cc index c0370f208..f56c9f6c3 100644 --- a/cpu/beta_cpu/alpha_full_cpu_builder.cc +++ b/cpu/beta_cpu/alpha_full_cpu_builder.cc @@ -71,7 +71,7 @@ class DerivAlphaFullCPU : public AlphaFullCPU BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) - Param cycle_time; + Param clock; Param numThreads; #ifdef FULL_SYSTEM @@ -164,7 +164,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) - INIT_PARAM(cycle_time, "cpu cycle time"), + INIT_PARAM(clock, "clock speed"), INIT_PARAM(numThreads, "number of HW thread contexts"), #ifdef FULL_SYSTEM @@ -298,7 +298,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) AlphaSimpleParams params; - params.cycleTime = cycle_time; + params.clock = clock; params.name = getInstanceName(); params.numberOfThreads = actual_num_threads; diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 06fee208d..f20b537f2 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -831,7 +831,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) SimObjectParam workload; #endif // FULL_SYSTEM - Param cycle_time; + Param clock; SimObjectParam icache; SimObjectParam dcache; @@ -863,7 +863,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM - INIT_PARAM(cycle_time, "cpu cycle time"), + INIT_PARAM(clock, "clock speed"), INIT_PARAM(icache, "L1 instruction cache object"), INIT_PARAM(dcache, "L1 data cache object"), INIT_PARAM(defer_registration, "defer system registration (for sampling)"), @@ -889,7 +889,7 @@ CREATE_SIM_OBJECT(SimpleCPU) params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; params->deferRegistration = defer_registration; - params->cycleTime = cycle_time; + params->clock = clock; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; params->icache_interface = (icache) ? icache->getInterface() : NULL; diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index ae044427e..35d9020db 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -99,7 +99,7 @@ IdeController::IdeController(Params *p) params()->host_bus, params()->host_bus, 1, true); - pioLatency = params()->pio_latency * params()->host_bus->clockRatio; + pioLatency = params()->pio_latency * params()->host_bus->clockRate; } // setup the disks attached to controller diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 65a162148..637cd7825 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -94,7 +94,7 @@ NSGigE::NSGigE(Params *p) : PciDev(p), ioEnable(false), txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size), txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL), - txXferLen(0), rxXferLen(0), cycleTime(p->cycle_time), + txXferLen(0), rxXferLen(0), clock(p->clock), txState(txIdle), txEnable(false), CTDD(false), txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle), rxEnable(false), CRDD(false), rxPktBytes(0), @@ -115,7 +115,7 @@ NSGigE::NSGigE(Params *p) p->header_bus, this, &NSGigE::cacheAccess); - pioLatency = p->pio_latency * p->header_bus->clockRatio; + pioLatency = p->pio_latency * p->header_bus->clockRate; if (p->payload_bus) dmaInterface = new DMAInterface(name() + ".dma", @@ -132,7 +132,7 @@ NSGigE::NSGigE(Params *p) p->payload_bus, this, &NSGigE::cacheAccess); - pioLatency = p->pio_latency * p->payload_bus->clockRatio; + pioLatency = p->pio_latency * p->payload_bus->clockRate; dmaInterface = new DMAInterface(name() + ".dma", p->payload_bus, @@ -2689,7 +2689,7 @@ REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt) BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param addr; - Param cycle_time; + Param clock; Param tx_delay; Param rx_delay; Param intr_delay; @@ -2723,7 +2723,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(addr, "Device Address"), - INIT_PARAM(cycle_time, "State machine processor frequency"), + INIT_PARAM(clock, "State machine processor frequency"), INIT_PARAM(tx_delay, "Transmit Delay"), INIT_PARAM(rx_delay, "Receive Delay"), INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"), @@ -2769,7 +2769,7 @@ CREATE_SIM_OBJECT(NSGigE) params->deviceNum = pci_dev; params->functionNum = pci_func; - params->cycle_time = cycle_time; + params->clock = clock; params->intr_delay = intr_delay; params->pmem = physmem; params->tx_delay = tx_delay; diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cbb7185e7..302aa5a89 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -176,8 +176,8 @@ class NSGigE : public PciDev ns_desc rxDescCache; /* state machine cycle time */ - Tick cycleTime; - inline Tick cycles(int numCycles) const { return numCycles * cycleTime; } + Tick clock; + inline Tick cycles(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; @@ -328,7 +328,7 @@ class NSGigE : public PciDev HierParams *hier; Bus *header_bus; Bus *payload_bus; - Tick cycle_time; + Tick clock; Tick intr_delay; Tick tx_delay; Tick rx_delay; diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 2cbd5adc0..fd0732d50 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -59,7 +59,7 @@ PciConfigAll::PciConfigAll(const string &name, pioInterface = newPioInterface(name, hier, bus, this, &PciConfigAll::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } // Make all the pointers to devices null diff --git a/dev/sinic.cc b/dev/sinic.cc index 1f7fceebe..5125a1d68 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -98,7 +98,7 @@ Device::Device(Params *p) pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this, &Device::cacheAccess); - pioLatency = p->pio_latency * p->io_bus->clockRatio; + pioLatency = p->pio_latency * p->io_bus->clockRate; if (p->payload_bus) dmaInterface = new DMAInterface(p->name + ".dma", p->io_bus, @@ -112,7 +112,7 @@ Device::Device(Params *p) pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this, &Device::cacheAccess); - pioLatency = p->pio_latency * p->payload_bus->clockRatio; + pioLatency = p->pio_latency * p->payload_bus->clockRate; dmaInterface = new DMAInterface(p->name + ".dma", p->payload_bus, p->payload_bus, 1, diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 2fb293fbf..a10dba082 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -59,7 +59,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiCChip::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } drir = 0; diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 895888a09..2e12b41ea 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -175,7 +175,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiIO::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } // set the back pointer from tsunami to myself diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index f846725f9..f8bec77c0 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -65,7 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiPChip::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } diff --git a/dev/uart.cc b/dev/uart.cc index caa169a2e..c04a5d066 100644 --- a/dev/uart.cc +++ b/dev/uart.cc @@ -109,7 +109,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &Uart::cacheAccess); pioInterface->addAddrRange(RangeSize(addr, size)); - pioLatency = pio_latency * bus->clockRatio; + pioLatency = pio_latency * bus->clockRate; } readAddr = 0; diff --git a/python/m5/config.py b/python/m5/config.py index 0aac595b1..f7b3f93ab 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -1096,12 +1096,20 @@ def tick_check(float_ticks): err = (float_ticks - int_ticks) / float_ticks if err > frequency_tolerance: print >> sys.stderr, "Warning: rounding error > tolerance" + print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks) + #raise ValueError return int_ticks # superclass for "numeric" parameter values, to emulate math # operations in a type-safe way. e.g., a Latency times an int returns # a new Latency object. class NumericParamValue(ParamValue): + def __str__(self): + return str(self.value) + + def __float__(self): + return float(self.value) + def __mul__(self, other): newobj = self.__class__(self) newobj.value *= other @@ -1109,27 +1117,31 @@ class NumericParamValue(ParamValue): __rmul__ = __mul__ + def __div__(self, other): + newobj = self.__class__(self) + newobj.value /= other + return newobj + + +def getLatency(value): + if isinstance(value, Latency) or isinstance(value, Clock): + return value.value + elif isinstance(value, Frequency) or isinstance(value, RootClock): + return 1 / value.value + elif isinstance(value, str): + try: + return toLatency(value) + except ValueError: + try: + return 1 / toFrequency(value) + except ValueError: + pass # fall through + raise ValueError, "Invalid Frequency/Latency value '%s'" % value + + class Latency(NumericParamValue): def __init__(self, value): - if isinstance(value, Latency): - self.value = value.value - elif isinstance(value, Frequency): - self.value = 1 / value.value - elif isinstance(value, str): - try: - self.value = toLatency(value) - except ValueError: - try: - freq = toFrequency(value) - except ValueError: - raise ValueError, "Latency value '%s' is neither " \ - "frequency nor period" % value - self.value = 1 / freq - elif value == 0: - # the one unitless value that's OK... - self.value = value - else: - raise ValueError, "Invalid Latency value '%s'" % value + self.value = getLatency(value) def __getattr__(self, attr): if attr in ('latency', 'period'): @@ -1138,31 +1150,13 @@ class Latency(NumericParamValue): return Frequency(self) raise AttributeError, "Latency object has no attribute '%s'" % attr - def __str__(self): - return str(self.value) - # convert latency to ticks def ini_str(self): return str(tick_check(self.value * ticks_per_sec)) class Frequency(NumericParamValue): def __init__(self, value): - if isinstance(value, Frequency): - self.value = value.value - elif isinstance(value, Latency): - self.value = 1 / value.value - elif isinstance(value, str): - try: - self.value = toFrequency(value) - except ValueError: - try: - freq = toLatency(value) - except ValueError: - raise ValueError, "Frequency value '%s' is neither " \ - "frequency nor period" % value - self.value = 1 / freq - else: - raise ValueError, "Invalid Frequency value '%s'" % value + self.value = 1 / getLatency(value) def __getattr__(self, attr): if attr == 'frequency': @@ -1171,21 +1165,44 @@ class Frequency(NumericParamValue): return Latency(self) raise AttributeError, "Frequency object has no attribute '%s'" % attr - def __str__(self): - return str(self.value) - - def __float__(self): - return float(self.value) - # convert frequency to ticks per period def ini_str(self): return self.period.ini_str() -# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz) -class RootFrequency(Frequency): +# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz). +# We can't inherit from Frequency because we don't want it to be directly +# assignable to a regular Frequency parameter. +class RootClock(ParamValue): + def __init__(self, value): + self.value = 1 / getLatency(value) + + def __getattr__(self, attr): + if attr == 'frequency': + return Frequency(self) + if attr in ('latency', 'period'): + return Latency(self) + raise AttributeError, "Frequency object has no attribute '%s'" % attr + def ini_str(self): return str(tick_check(self.value)) +# A generic frequency and/or Latency value. Value is stored as a latency, +# but to avoid ambiguity this object does not support numeric ops (* or /). +# An explicit conversion to a Latency or Frequency must be made first. +class Clock(ParamValue): + def __init__(self, value): + self.value = getLatency(value) + + def __getattr__(self, attr): + if attr == 'frequency': + return Frequency(self) + if attr in ('latency', 'period'): + return Latency(self) + raise AttributeError, "Frequency object has no attribute '%s'" % attr + + def ini_str(self): + return self.period.ini_str() + class NetworkBandwidth(float,ParamValue): def __new__(cls, value): val = toNetworkBandwidth(value) / 8.0 @@ -1223,7 +1240,7 @@ AllMemory = AddrRange(0, MaxAddr) # script once config is built. def instantiate(root): global ticks_per_sec - ticks_per_sec = float(root.frequency) + ticks_per_sec = float(root.clock.frequency) root.print_ini() noDot = True # temporary until we fix dot if not noDot: @@ -1246,7 +1263,7 @@ __all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam', 'Int32', 'UInt32', 'Int64', 'UInt64', 'Counter', 'Addr', 'Tick', 'Percent', 'TcpPort', 'UdpPort', 'EthernetAddr', - 'MemorySize', 'Latency', 'Frequency', 'RootFrequency', + 'MemorySize', 'Latency', 'Frequency', 'RootClock', 'Clock', 'NetworkBandwidth', 'MemoryBandwidth', 'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory', 'Null', 'NULL', diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index d4fa13d3b..0dc436434 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -25,4 +25,4 @@ class BaseCPU(SimObject): defer_registration = Param.Bool(False, "defer registration with system (for sampling)") - cycle_time = Param.Latency(Parent.frequency.latency, "clock speed") + clock = Param.Clock(Parent.clock, "clock speed") diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py index d311969fa..79d21572a 100644 --- a/python/m5/objects/BaseCache.py +++ b/python/m5/objects/BaseCache.py @@ -11,7 +11,7 @@ class BaseCache(BaseMem): block_size = Param.Int("block size in bytes") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") - compression_latency = Param.Latency(0, + compression_latency = Param.Latency('0ns', "Latency in cycles of compression algorithm") do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") diff --git a/python/m5/objects/BaseSystem.py b/python/m5/objects/BaseSystem.py index 48c70e44f..457eadb36 100644 --- a/python/m5/objects/BaseSystem.py +++ b/python/m5/objects/BaseSystem.py @@ -2,7 +2,7 @@ from m5 import * class BaseSystem(SimObject): type = 'BaseSystem' abstract = True - boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency, + boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, "boot processor frequency") memctrl = Param.MemoryController(Parent.any, "memory controller") physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py index 1ed87d2e7..26509d7d2 100644 --- a/python/m5/objects/Bus.py +++ b/python/m5/objects/Bus.py @@ -3,5 +3,5 @@ from BaseHier import BaseHier class Bus(BaseHier): type = 'Bus' - clock_ratio = Param.Frequency("ratio of CPU to bus frequency") + clock = Param.Clock("bus frequency") width = Param.Int("bus width in bytes") diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 69dec1528..c89505477 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -58,7 +58,7 @@ class NSGigE(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + clock = Param.Clock('100MHz', "State machine processor frequency") dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") @@ -95,7 +95,7 @@ class Sinic(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + clock = Param.Clock('100MHz', "State machine processor frequency") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index 78d5388f0..79e3721fc 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -6,7 +6,7 @@ from Trace import Trace class Root(SimObject): type = 'Root' - frequency = Param.RootFrequency('200MHz', "tick frequency") + clock = Param.RootClock('200MHz', "tick frequency") output_file = Param.String('cout', "file to dump simulator output to") checkpoint = Param.String('', "checkpoint file to load") # hier = Param.HierParams(HierParams(do_data = False, do_events = True), diff --git a/sim/universe.cc b/sim/universe.cc index ecf54c2e7..981a8ebae 100644 --- a/sim/universe.cc +++ b/sim/universe.cc @@ -85,14 +85,14 @@ class Root : public SimObject BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root) - Param frequency; + Param clock; Param output_file; END_DECLARE_SIM_OBJECT_PARAMS(Root) BEGIN_INIT_SIM_OBJECT_PARAMS(Root) - INIT_PARAM(frequency, "tick frequency"), + INIT_PARAM(clock, "tick frequency"), INIT_PARAM(output_file, "file to dump simulator output to") END_INIT_SIM_OBJECT_PARAMS(Root) @@ -109,7 +109,7 @@ CREATE_SIM_OBJECT(Root) Root *root = new Root(getInstanceName()); using namespace Clock; - Frequency = frequency; + Frequency = clock; Float::s = static_cast(Frequency); Float::ms = Float::s / 1.0e3; Float::us = Float::s / 1.0e6;