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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

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X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
sim_seconds 5.172174 # Number of seconds simulated
sim_ticks 5172174196500 # Number of ticks simulated
final_tick 5172174196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
host_inst_rate 197854 # Simulator instruction rate (inst/s)
host_op_rate 391125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2509698416 # Simulator tick rate (ticks/s)
host_mem_usage 367744 # Number of bytes of host memory used
host_seconds 2060.87 # Real time elapsed on the host
sim_insts 407751921 # Number of instructions simulated
sim_ops 806059216 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2469504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.bytes_read::cpu.inst 1070336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10446016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13989120 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1070336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1070336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9206912 # Number of bytes written to this memory
system.physmem.bytes_written::total 9206912 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.num_reads::cpu.inst 16724 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 163219 # Number of read requests responded to by this memory
system.physmem.num_reads::total 218580 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143858 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143858 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 477460 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 544 # Total read bandwidth from this memory (bytes/s)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.bw_read::cpu.inst 206941 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2019657 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2704688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 206941 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 206941 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1780085 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1780085 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1780085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 477460 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 544 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.bw_total::cpu.inst 206941 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2019657 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4484774 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 107330 # number of replacements
system.l2c.tagsinuse 64831.864344 # Cycle average of tags in use
system.l2c.total_refs 3982185 # Total number of references to valid blocks.
system.l2c.sampled_refs 171532 # Sample count of references to valid blocks.
system.l2c.avg_refs 23.215406 # Average number of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.occ_blocks::writebacks 50277.913573 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 9.980895 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.169682 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 3388.636576 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 11155.163618 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.767180 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.occ_percent::cpu.inst 0.051706 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.170214 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.989256 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 111938 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 8555 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 1051956 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1345107 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2517556 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1612922 # number of Writeback hits
system.l2c.Writeback_hits::total 1612922 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 325 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 325 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 163659 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 163659 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 111938 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 8555 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 1051956 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1508766 # number of demand (read+write) hits
system.l2c.demand_hits::total 2681215 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 111938 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 8555 # number of overall hits
system.l2c.overall_hits::cpu.inst 1051956 # number of overall hits
system.l2c.overall_hits::cpu.data 1508766 # number of overall hits
system.l2c.overall_hits::total 2681215 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_misses::cpu.inst 16726 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 35201 # number of ReadReq misses
system.l2c.ReadReq_misses::total 51978 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 128962 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 128962 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_misses::cpu.inst 16726 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 164163 # number of demand (read+write) misses
system.l2c.demand_misses::total 180940 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 44 # number of overall misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_misses::cpu.inst 16726 # number of overall misses
system.l2c.overall_misses::cpu.data 164163 # number of overall misses
system.l2c.overall_misses::total 180940 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2308000 # number of ReadReq miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_miss_latency::cpu.inst 887926997 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 1876685493 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2767284490 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 37648500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 37648500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6721908000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6721908000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker 2308000 # number of demand (read+write) miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_miss_latency::cpu.inst 887926997 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 8598593493 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9489192490 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker 2308000 # number of overall miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_miss_latency::cpu.inst 887926997 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 8598593493 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9489192490 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker 111982 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 8562 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 1068682 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1380308 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2569534 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1612922 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1612922 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 292621 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 292621 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 111982 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 8562 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 1068682 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1672929 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2862155 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 111982 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 8562 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 1068682 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1672929 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2862155 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000393 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000818 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.015651 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.025502 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020229 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.821722 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.821722 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.440713 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.440713 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000393 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000818 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.015651 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.098129 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.063218 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000393 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000818 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.015651 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.098129 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.063218 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52454.545455 # average ReadReq miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53086.631412 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 53313.414193 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53239.533841 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25132.510013 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 25132.510013 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.168065 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52123.168065 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52443.862551 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52454.545455 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_avg_miss_latency::cpu.inst 53086.631412 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52378.389119 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52443.862551 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.writebacks::writebacks 97191 # number of writebacks
system.l2c.writebacks::total 97191 # number of writebacks
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_misses::cpu.inst 16724 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 35200 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 51975 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 128962 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 128962 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_mshr_misses::cpu.inst 16724 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 164162 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 180937 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_mshr_misses::cpu.inst 16724 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 164162 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 180937 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1774500 # number of ReadReq MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 683968997 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1446479000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2132502497 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60328500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 60328500 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5168491500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5168491500 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1774500 # number of demand (read+write) MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_mshr_miss_latency::cpu.inst 683968997 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 6614970500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 7300993997 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1774500 # number of overall MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_mshr_miss_latency::cpu.inst 683968997 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 6614970500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 7300993997 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 88673683000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 88673683000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2309054000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2309054000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 90982737000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 90982737000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025502 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020227 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821722 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.821722 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440713 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.440713 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.063217 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.063217 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40897.452583 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41093.153409 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 41029.389072 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40272.696929 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40272.696929 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40077.631395 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40077.631395 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.replacements 47572 # number of replacements
system.iocache.tagsinuse 0.197153 # Cycle average of tags in use
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.sampled_refs 47588 # Sample count of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.warmup_cycle 5000849406000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.197153 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.012322 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.012322 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
system.iocache.overall_misses::total 47627 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136172932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 136172932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6920648160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 6920648160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 7056821092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7056821092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 7056821092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7056821092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 150135.536935 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 148130.311644 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 148168.498793 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 148168.498793 # average overall miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
X86 Regression: update stats due to cc register split
2012-05-22 18:38:04 +02:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88977000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 88977000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4490887946 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4490887946 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4579864946 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4579864946 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.numCycles 475031565 # number of cpu cycles simulated
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.BPredUnit.lookups 86684856 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 86684856 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1176632 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 82122133 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 79543196 # Number of BTB hits
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.fetch.icacheStallCycles 31269539 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 428184771 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86684856 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79543196 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 164289785 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5325147 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 164614 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 76824227 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 37234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 45914 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9378048 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 536886 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 4957 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 276741596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.053538 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.401990 # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.fetch.rateDist::0 112886536 40.79% 40.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1619655 0.59% 41.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71962795 26.00% 67.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 983886 0.36% 67.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1644119 0.59% 68.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2486257 0.90% 69.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1139995 0.41% 69.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1450599 0.52% 70.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 82567754 29.84% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.fetch.rateDist::total 276741596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.182482 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.901382 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 35010017 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 74311956 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 159865423 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3444346 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4109854 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 841785392 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 993 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4109854 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 38173067 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 41532647 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 11823127 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 159691932 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 21410969 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 837988743 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10561 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 14331873 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3961467 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 8380256 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1328629800 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2380702001 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2380701417 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 584 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1282020322 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 46609471 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 469457 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 477289 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 33840968 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17569417 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10446486 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1246814 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1007946 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 831743249 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1259421 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 823989117 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 123035 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26027822 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 53490149 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 209479 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 276741596 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.977468 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.409448 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iq.issued_per_cycle::0 86092872 31.11% 31.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 17946523 6.48% 37.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 12957239 4.68% 42.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7826219 2.83% 45.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 76249367 27.55% 72.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3109383 1.12% 73.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 71927366 25.99% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 520136 0.19% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 112491 0.04% 100.00% # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iq.issued_per_cycle::total 276741596 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iq.fu_full::IntAlu 163103 18.01% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 583729 64.45% 82.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 158924 17.55% 100.00% # attempts to use FU when none available
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iq.FU_type_0::No_OpClass 296041 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 796340985 96.64% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 17916922 2.17% 98.85% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9435169 1.15% 100.00% # Type of FU issued
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iq.FU_type_0::total 823989117 # Type of FU issued
system.cpu.iq.rate 1.734599 # Inst issue rate
system.cpu.iq.fu_busy_cnt 905756 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1925886604 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 859041376 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 819484767 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 824598744 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1578458 # Number of loads that had data forwarded from stores
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 3618337 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20593 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12016 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2047079 # Number of stores squashed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1917340 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4451 # Number of times an access to memory failed due to the cache being blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iew.iewSquashCycles 4109854 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 27168187 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1772103 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 833002670 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 300864 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17569417 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10446486 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 728436 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 974858 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 15486 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12016 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 697910 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 625387 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1323297 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 822095189 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17489841 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1893927 # Number of squashed instructions skipped in execute
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iew.exec_refs 26681633 # number of memory reference insts executed
system.cpu.iew.exec_branches 83151598 # Number of branches executed
system.cpu.iew.exec_stores 9191792 # Number of stores executed
system.cpu.iew.exec_rate 1.730612 # Inst execution rate
system.cpu.iew.wb_sent 821608460 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 819484817 # cumulative count of insts written-back
system.cpu.iew.wb_producers 640296111 # num instructions producing a value
system.cpu.iew.wb_consumers 1828731330 # num instructions consuming a value
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.iew.wb_rate 1.725117 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.350131 # average fanout of values written-back
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.commitCommittedInsts 407751921 # The number of committed instructions
system.cpu.commit.commitCommittedOps 806059216 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26839677 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1049940 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1181775 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 272647181 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.956419 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.843352 # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.committed_per_cycle::0 98573076 36.15% 36.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13223290 4.85% 41.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4246957 1.56% 42.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 75817327 27.81% 70.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2710299 0.99% 71.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1789124 0.66% 72.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1087866 0.40% 72.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71017917 26.05% 98.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4181325 1.53% 100.00% # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.committed_per_cycle::total 272647181 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407751921 # Number of instructions committed
system.cpu.commit.committedOps 806059216 # Number of ops (including micro ops) committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.refs 22350484 # Number of memory references committed
system.cpu.commit.loads 13951077 # Number of loads committed
system.cpu.commit.membars 471695 # Number of memory barriers committed
system.cpu.commit.branches 82163258 # Number of branches committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.int_insts 735013406 # Number of committed integer instructions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.commit.bw_lim_events 4181325 # number cycles where commit BW limit reached
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.rob.rob_reads 1101286190 # The number of ROB reads
system.cpu.rob.rob_writes 1669922447 # The number of ROB writes
system.cpu.timesIdled 1659907 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 198289969 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9869314281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407751921 # Number of Instructions Simulated
system.cpu.committedOps 806059216 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407751921 # Number of Instructions Simulated
system.cpu.cpi 1.165001 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.165001 # CPI: Total CPI of All Threads
system.cpu.ipc 0.858368 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.858368 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2053713870 # number of integer regfile reads
system.cpu.int_regfile_writes 1297159076 # number of integer regfile writes
system.cpu.fp_regfile_reads 50 # number of floating regfile reads
system.cpu.misc_regfile_reads 265135377 # number of misc regfile reads
system.cpu.misc_regfile_writes 402339 # number of misc regfile writes
system.cpu.icache.replacements 1068223 # number of replacements
system.cpu.icache.tagsinuse 510.418027 # Cycle average of tags in use
system.cpu.icache.total_refs 8239400 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1068735 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.709488 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 57281567000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.418027 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996910 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996910 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 8239400 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8239400 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8239400 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8239400 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8239400 # number of overall hits
system.cpu.icache.overall_hits::total 8239400 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1138645 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1138645 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1138645 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1138645 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1138645 # number of overall misses
system.cpu.icache.overall_misses::total 1138645 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18814976480 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18814976480 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18814976480 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18814976480 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18814976480 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18814976480 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9378045 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9378045 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9378045 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9378045 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9378045 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9378045 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121416 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.121416 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.121416 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.121416 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.121416 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.121416 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16524.005709 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16524.005709 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3200487 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.icache.blocked::no_mshrs 386 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 8291.417098 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69787 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 69787 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 69787 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 69787 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 69787 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 69787 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1068858 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1068858 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1068858 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1068858 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1068858 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1068858 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14704003987 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14704003987 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14704003987 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14704003987 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14704003987 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14704003987 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113975 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.113975 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.113975 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.itb_walker_cache.replacements 10021 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.028958 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 32291 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 10034 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 3.218158 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5136098133000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028958 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376810 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.376810 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32310 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 32310 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32313 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 32313 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32313 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 32313 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10911 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 10911 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10911 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 10911 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10911 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 10911 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183901500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183901500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183901500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 183901500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183901500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 183901500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43221 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43224 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 43224 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43224 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 43224 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.252447 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.252447 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.252429 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.252429 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.252429 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.252429 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 1563 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1563 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10911 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10911 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10911 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 10911 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10911 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 10911 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 150559535 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 150559535 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 150559535 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 150559535 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 150559535 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 150559535 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.252447 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.252447 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.252429 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.252429 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dtb_walker_cache.replacements 116564 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 12.971477 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 137576 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 116580 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.180100 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5113123336000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.971477 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810717 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.810717 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137576 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 137576 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137576 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 137576 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137576 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 137576 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117614 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 117614 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117614 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 117614 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117614 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 117614 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2140596500 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2140596500 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2140596500 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 2140596500 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2140596500 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 2140596500 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255190 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 255190 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255190 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 255190 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255190 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 255190 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.460888 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.460888 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.460888 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.460888 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.460888 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.460888 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 39184 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 39184 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117614 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117614 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117614 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 117614 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117614 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 117614 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1785080011 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1785080011 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1785080011 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.460888 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.460888 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.460888 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dcache.replacements 1673020 # number of replacements
system.cpu.dcache.tagsinuse 511.997654 # Cycle average of tags in use
system.cpu.dcache.total_refs 19008279 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1673532 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.358181 # Average number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dcache.occ_blocks::cpu.data 511.997654 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10932679 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10932679 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8073031 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8073031 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19005710 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19005710 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19005710 # number of overall hits
system.cpu.dcache.overall_hits::total 19005710 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2430444 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2430444 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 317095 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 317095 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2747539 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2747539 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2747539 # number of overall misses
system.cpu.dcache.overall_misses::total 2747539 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 45216991000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 45216991000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10602716492 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10602716492 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 55819707492 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 55819707492 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 55819707492 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 55819707492 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13363123 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13363123 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8390126 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8390126 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21753249 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21753249 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21753249 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21753249 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181877 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.181877 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037794 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037794 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.126305 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.126305 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.126305 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.126305 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18604.415901 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20316.256654 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20316.256654 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 27551492 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dcache.blocked::no_mshrs 4916 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5604.453214 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.dcache.writebacks::writebacks 1572175 # number of writebacks
system.cpu.dcache.writebacks::total 1572175 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1048961 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1048961 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22710 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 22710 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1071671 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1071671 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1071671 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1071671 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381483 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1381483 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294385 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 294385 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1675868 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1675868 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1675868 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1675868 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23305790513 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23305790513 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9339566493 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9339566493 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32645357006 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32645357006 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32645357006 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32645357006 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96733569500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96733569500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2477085000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2477085000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99210654500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99210654500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103380 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103380 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035087 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035087 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink