gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.852840                       # Number of seconds simulated
sim_ticks                                2852839554500                       # Number of ticks simulated
final_tick                               2852839554500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 169032                       # Simulator instruction rate (inst/s)
host_op_rate                                   204382                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4294589830                       # Simulator tick rate (ticks/s)
host_mem_usage                                 620820                       # Number of bytes of host memory used
host_seconds                                   664.29                       # Real time elapsed on the host
sim_insts                                   112285680                       # Number of instructions simulated
sim_ops                                     135768245                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         7680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1672128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9190636                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10871532                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1672128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1672128                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7983360                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8000884                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          120                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26127                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144125                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170389                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124740                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               129121                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2692                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               586128                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3221575                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3810776                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          586128                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             586128                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2798391                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2804533                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2798391                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2692                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              586128                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3227717                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6615309                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170389                       # Number of read requests accepted
system.physmem.writeReqs                       165345                       # Number of write requests accepted
system.physmem.readBursts                      170389                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     165345                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10897024                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7872                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9054784                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10871532                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10319220                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      123                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23835                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4587                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10917                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10861                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10721                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10725                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13339                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10813                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11142                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10985                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10153                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10280                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10274                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9203                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10314                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10760                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10035                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9744                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9017                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9225                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9344                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9210                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8591                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8923                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9235                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9154                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8919                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8830                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8770                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8263                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8824                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8884                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8238                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8054                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          37                       # Number of times write queue was full causing retry
system.physmem.totGap                    2852839149500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169832                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 160964                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    163637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      6336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      488                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       43                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        61975                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      321.932134                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.780856                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     337.844354                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22404     36.15%     36.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14558     23.49%     59.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6628     10.69%     70.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3590      5.79%     76.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2633      4.25%     80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1568      2.53%     82.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1136      1.83%     84.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1187      1.92%     86.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8271     13.35%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          61975                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5903                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.841945                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      583.033382                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5902     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5903                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5903                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.967644                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.368451                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       42.492651                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            5572     94.39%     94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              86      1.46%     95.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              22      0.37%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              13      0.22%     96.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              26      0.44%     96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             23      0.39%     97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            23      0.39%     97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            20      0.34%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159             7      0.12%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             2      0.03%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            23      0.39%     98.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            13      0.22%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            11      0.19%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             2      0.03%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.03%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             3      0.05%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             2      0.03%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             6      0.10%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             7      0.12%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             5      0.08%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             2      0.03%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            15      0.25%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             4      0.07%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.02%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             3      0.05%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             2      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5903                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1723482630                       # Total ticks spent queuing
system.physmem.totMemAccLat                4915970130                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    851330000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10122.29                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28872.29                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.62                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.62                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140451                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109320                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.25                       # Row buffer hit rate for writes
system.physmem.avgGap                      8497319.75                       # Average gap between requests
system.physmem.pageHitRate                      80.11                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  245019600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  133691250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 698123400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                471089520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186333332640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83679210810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1638298500750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1909858967970                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.459893                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2725317218918                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95262440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32255883582                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  223511400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  121955625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 629943600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                445707360                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186333332640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82264054140                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1639539866250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1909558371015                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.354525                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2727396126418                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95262440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30180892082                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             157                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31043514                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16869099                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2536489                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18574786                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13386311                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             72.067108                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7804422                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1529182                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                     65823                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                65823                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43117                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22706                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        65823                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           65823    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        65823                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7829                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8717.816397                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7451.711579                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         6121     78.18%     78.18% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767         1701     21.73%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151            1      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7829                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    262515000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       262515000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    262515000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6444     82.31%     82.31% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1385     17.69%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7829                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65823                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65823                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7829                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7829                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        73652                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24809902                       # DTB read hits
system.cpu.dtb.read_misses                      58990                       # DTB read misses
system.cpu.dtb.write_hits                    19469042                       # DTB write hits
system.cpu.dtb.write_misses                      6833                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4354                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1238                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1767                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       748                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24868892                       # DTB read accesses
system.cpu.dtb.write_accesses                19475875                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44278944                       # DTB hits
system.cpu.dtb.misses                           65823                       # DTB misses
system.cpu.dtb.accesses                      44344767                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      5435                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5435                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5114                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5435                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5435    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5435                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3183                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 11172.007540                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8898.591631                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7073.724538                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1308     41.09%     41.09% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383         1159     36.41%     77.51% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          715     22.46%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3183                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    262109500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       262109500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    262109500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2873     90.26%     90.26% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.74%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3183                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5435                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5435                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3183                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3183                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         8618                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57700454                       # ITB inst hits
system.cpu.itb.inst_misses                       5435                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2972                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8445                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57705889                       # ITB inst accesses
system.cpu.itb.hits                          57700454                       # DTB hits
system.cpu.itb.misses                            5435                       # DTB misses
system.cpu.itb.accesses                      57705889                       # DTB accesses
system.cpu.numCycles                        315730000                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112285680                       # Number of instructions committed
system.cpu.committedOps                     135768245                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7761547                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5390009685                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.811846                       # CPI: cycles per instruction
system.cpu.ipc                               0.355638                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
system.cpu.tickCycles                       227805023                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        87924977                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            842413                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.947858                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42688411                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            842925                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.643190                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         313221250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.947858                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999898                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999898                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176513094                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176513094                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23118388                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23118388                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18306742                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18306742                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356409                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356409                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443709                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443709                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460231                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460231                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41425130                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41425130                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41781539                       # number of overall hits
system.cpu.dcache.overall_hits::total        41781539                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       491811                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        491811                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       547829                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       547829                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       170067                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       170067                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22347                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22347                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1039640                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1039640                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1209707                       # number of overall misses
system.cpu.dcache.overall_misses::total       1209707                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7276171447                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7276171447                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  23463335520                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  23463335520                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    282730000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    282730000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  30739506967                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  30739506967                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  30739506967                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  30739506967                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23610199                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23610199                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18854571                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18854571                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       526476                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       526476                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466056                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466056                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460233                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460233                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42464770                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42464770                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42991246                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42991246                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020830                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.020830                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029056                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029056                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323029                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.323029                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047949                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047949                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024482                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024482                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028138                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028138                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.649666                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.649666                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42829.670426                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42829.670426                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12651.810086                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12651.810086                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29567.453125                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29567.453125                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25410.704383                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25410.704383                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          271                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.318182                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       697807                       # number of writebacks
system.cpu.dcache.writebacks::total            697807                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        74753                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        74753                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249005                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249005                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14114                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14114                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       323758                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       323758                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       323758                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       323758                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417058                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       417058                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298824                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298824                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121668                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121668                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8233                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8233                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       715882                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       715882                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       837550                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       837550                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5703692140                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5703692140                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12347213418                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12347213418                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1562689830                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1562689830                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    105383000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    105383000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18050905558                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  18050905558                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19613595388                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19613595388                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5837245750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5837245750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4509635000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4509635000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10346880750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10346880750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017664                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017664                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015849                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015849                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231099                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231099                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017665                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017665                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016858                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016858                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019482                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019482                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13676.016621                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13676.016621                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41319.349912                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41319.349912                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12843.885245                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12843.885245                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12800.072877                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12800.072877                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25214.917484                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25214.917484                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23417.820295                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23417.820295                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187523.957530                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187523.957530                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163493.274843                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163493.274843                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176234.108600                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176234.108600                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           2897053                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.399913                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54794053                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2897565                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.910379                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       15532087250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.399913                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998828                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998828                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          196                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60589206                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60589206                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     54794053                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54794053                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54794053                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54794053                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54794053                       # number of overall hits
system.cpu.icache.overall_hits::total        54794053                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2897577                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2897577                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2897577                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2897577                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2897577                       # number of overall misses
system.cpu.icache.overall_misses::total       2897577                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39289899153                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39289899153                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39289899153                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39289899153                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39289899153                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39289899153                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57691630                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57691630                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57691630                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57691630                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57691630                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57691630                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050225                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050225                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050225                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050225                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050225                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050225                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.570342                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13559.570342                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.570342                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13559.570342                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.570342                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13559.570342                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897577                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2897577                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2897577                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2897577                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2897577                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2897577                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3172                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3172                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3172                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3172                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  34933961847                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  34933961847                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  34933961847                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  34933961847                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  34933961847                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  34933961847                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    247386750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    247386750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    247386750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    247386750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050225                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050225                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050225                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050225                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050225                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050225                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.266959                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12056.266959                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.266959                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12056.266959                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.266959                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12056.266959                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            97102                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65057.867689                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4043768                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162361                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.906030                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 47470.110176                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    67.851294                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009474                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12225.097724                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5294.799022                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.724336                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001035                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.186540                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.080792                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992704                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65201                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           58                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2302                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6944                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55834                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000885                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994888                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         36586462                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        36586462                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69776                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4408                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      2874567                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       532630                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        3481381                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       697807                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       697807                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           52                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           52                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       164524                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       164524                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        69776                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4408                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2874567                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       697154                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3645905                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        69776                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4408                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2874567                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       697154                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3645905                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          120                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        22985                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        14324                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        37431                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2777                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2777                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131476                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131476                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          120                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22985                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       145800                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168907                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          120                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22985                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       145800                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168907                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     10600250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       179750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1839480250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1206111580                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3056371830                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1094965                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1094965                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10223101190                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10223101190                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     10600250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       179750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1839480250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11429212770                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13279473020                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     10600250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       179750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1839480250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11429212770                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13279473020                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        69896                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4410                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      2897552                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       546954                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      3518812                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       697807                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       697807                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2829                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2829                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296000                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296000                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69896                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4410                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2897552                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       842954                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3814812                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69896                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4410                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2897552                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       842954                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3814812                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000454                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.007933                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026189                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.010637                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.981619                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981619                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.444176                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.444176                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000454                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007933                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172963                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.044277                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000454                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007933                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172963                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.044277                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88335.416667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        89875                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80029.595388                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84202.148841                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81653.491224                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   394.297803                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   394.297803                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77756.405656                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77756.405656                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88335.416667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        89875                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80029.595388                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78389.662346                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78620.027708                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88335.416667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        89875                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80029.595388                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78389.662346                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78620.027708                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        88550                       # number of writebacks
system.cpu.l2cache.writebacks::total            88550                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           20                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          140                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           20                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          160                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          120                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        22965                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        14184                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        37271                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2777                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2777                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131476                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131476                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          120                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22965                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       145660                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168747                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          120                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22965                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       145660                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168747                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3172                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34300                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3172                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61883                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9096750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       154250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1550905750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1018516170                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2578672920                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     49510277                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     49510277                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       137000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       137000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8577805310                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8577805310                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9096750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       154250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1550905750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9596321480                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11156478230                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      9096750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       154250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1550905750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9596321480                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11156478230                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191729750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5400947000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5592676750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4150934000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4150934000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191729750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9551881000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9743610750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000454                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.007926                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025933                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010592                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.981619                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981619                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444176                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444176                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000454                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007926                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172797                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.044235                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000454                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007926                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172797                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.044235                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67533.453081                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71807.400592                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69187.113842                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17828.691754                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17828.691754                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.365983                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.365983                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67533.453081                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65881.652341                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66113.638939                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        77125                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67533.453081                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65881.652341                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66113.638939                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173507.677975                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163051.800292                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150488.851829                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162693.209109                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3578143                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3578049                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       697807                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2829                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2831                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296000                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296000                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5801472                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2506940                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14959                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       158425                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8481796                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185646272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98800797                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       279584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          284744293                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       61425                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4638617                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.029225                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.168438                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            4503052     97.08%     97.08% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             135565      2.92%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4638617                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3012663750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       211500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4356641403                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1341917112                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      10549250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      88533000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22790                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198836241                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36810509                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.031382                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270536492000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.031382                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064461                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064461                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29235877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29235877                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6642330855                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6642330855                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29235877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29235877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29235877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29235877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124939.645299                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124939.645299                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183368.232525                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183368.232525                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124939.645299                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124939.645299                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124939.645299                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124939.645299                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22431                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3441                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.518745                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16926877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16926877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4758664873                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4758664873                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16926877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16926877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16926877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16926877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72337.081197                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72337.081197                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               71805                       # Transaction distribution
system.membus.trans_dist::ReadResp              71805                       # Transaction distribution
system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
system.membus.trans_dist::Writeback            124740                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4587                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4589                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129666                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129666                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447521                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       555081                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 663968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16555296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16719005                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21354461                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              506                       # Total snoops (count)
system.membus.snoop_fanout::samples            394644                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  394644    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              394644                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90290000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1707500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1026254667                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          999643493                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37473491                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------