2014-07-23 23:09:05 +02:00
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---------- Begin Simulation Statistics ----------
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2015-03-19 13:41:32 +01:00
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sim_seconds 2.852832 # Number of seconds simulated
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sim_ticks 2852831758500 # Number of ticks simulated
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final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2014-07-23 23:09:05 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2015-03-19 13:41:32 +01:00
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host_inst_rate 111123 # Simulator instruction rate (inst/s)
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host_op_rate 134357 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2834419538 # Simulator tick rate (ticks/s)
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host_mem_usage 554504 # Number of bytes of host memory used
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host_seconds 1006.50 # Real time elapsed on the host
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sim_insts 111845135 # Number of instructions simulated
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sim_ops 135229426 # Number of ops (including micro ops) simulated
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2014-07-28 07:48:21 +02:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2015-03-19 13:41:32 +01:00
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system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory
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2014-12-02 12:08:25 +01:00
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system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory
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2014-10-30 05:18:29 +01:00
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory
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2015-01-04 20:02:12 +01:00
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system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory
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2014-12-02 12:08:25 +01:00
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system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory
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2014-10-30 05:18:29 +01:00
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory
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2015-01-04 20:02:12 +01:00
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system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
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2015-03-19 13:41:32 +01:00
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system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s)
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2014-12-02 12:08:25 +01:00
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system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
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2015-03-19 13:41:32 +01:00
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system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s)
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2014-12-02 12:08:25 +01:00
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system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
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2015-03-19 13:41:32 +01:00
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system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 170038 # Number of read requests accepted
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system.physmem.writeReqs 165152 # Number of write requests accepted
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system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue
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system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10711 # Per bank write bursts
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system.physmem.perBankRdBursts::1 10418 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10743 # Per bank write bursts
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system.physmem.perBankRdBursts::3 10617 # Per bank write bursts
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system.physmem.perBankRdBursts::4 13557 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10851 # Per bank write bursts
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system.physmem.perBankRdBursts::6 10986 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10951 # Per bank write bursts
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system.physmem.perBankRdBursts::8 10335 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10516 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10068 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9192 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10325 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10893 # Per bank write bursts
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system.physmem.perBankRdBursts::14 9864 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9921 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8907 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8809 # Per bank write bursts
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system.physmem.perBankWrBursts::2 9307 # Per bank write bursts
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system.physmem.perBankWrBursts::3 9147 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8787 # Per bank write bursts
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system.physmem.perBankWrBursts::5 9076 # Per bank write bursts
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system.physmem.perBankWrBursts::6 9209 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9123 # Per bank write bursts
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system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
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system.physmem.perBankWrBursts::9 9064 # Per bank write bursts
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system.physmem.perBankWrBursts::10 8553 # Per bank write bursts
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system.physmem.perBankWrBursts::11 8266 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8846 # Per bank write bursts
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system.physmem.perBankWrBursts::13 9045 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8063 # Per bank write bursts
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system.physmem.perBankWrBursts::15 8171 # Per bank write bursts
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2014-07-28 07:48:21 +02:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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2015-03-19 13:41:32 +01:00
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system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
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system.physmem.totGap 2852831352500 # Total gap between requests
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2014-07-28 07:48:21 +02:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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2014-10-30 05:18:29 +01:00
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system.physmem.readPktSize::2 541 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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2014-07-28 07:48:21 +02:00
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2015-03-19 13:41:32 +01:00
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system.physmem.readPktSize::6 169483 # Read request sizes (log2)
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2014-07-28 07:48:21 +02:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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2014-10-30 05:18:29 +01:00
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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2014-07-28 07:48:21 +02:00
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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2015-03-19 13:41:32 +01:00
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system.physmem.writePktSize::6 160771 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see
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2014-10-30 05:18:29 +01:00
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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2014-07-28 07:48:21 +02:00
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
2015-03-19 13:41:32 +01:00
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system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see
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|
|
system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 1723441444 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst
|
2014-12-02 12:08:25 +01:00
|
|
|
system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s
|
2014-12-02 12:08:25 +01:00
|
|
|
system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
2014-10-30 05:18:29 +01:00
|
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
|
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 140236 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 109426 # Number of row buffer hits during writes
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 8511087.30 # Average gap between requests
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_0.averagePower 669.450935 # Core power per rank (mW)
|
|
|
|
|
system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_1.averagePower 669.358845 # Core power per rank (mW)
|
|
|
|
|
system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2015-03-19 13:41:32 +01:00
|
|
|
system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-11-03 17:14:42 +01:00
|
|
|
system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
|
2014-07-23 23:09:05 +02:00
|
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
|
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.branchPred.lookups 31016169 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions.
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.walker.walks 66365 # Table walker walks requested
|
|
|
|
|
system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors
|
|
|
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate
|
|
|
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate
|
|
|
|
|
system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
|
|
|
|
|
system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
|
|
|
|
|
system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated
|
|
|
|
|
system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated
|
|
|
|
|
system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated
|
|
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.read_hits 24709745 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 59626 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_hits 19412201 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 6739 # DTB write misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 24769371 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 19418940 # DTB write accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dtb.hits 44121946 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 66365 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 44188311 # DTB accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.walker.walks 5448 # Table walker walks requested
|
|
|
|
|
system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors
|
|
|
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
|
|
|
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate
|
|
|
|
|
system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency
|
|
|
|
|
system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
|
|
|
|
|
system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
|
|
|
|
|
system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
|
|
|
|
|
system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
|
|
|
|
|
system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst
|
|
|
|
|
system.cpu.itb.inst_hits 57588649 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 5448 # ITB inst misses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.itb.inst_accesses 57594097 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 57588649 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 5448 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 57594097 # DTB accesses
|
|
|
|
|
system.cpu.numCycles 315565701 # number of cpu cycles simulated
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.committedInsts 111845135 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
|
|
|
system.cpu.cpi 2.821452 # CPI: cycles per instruction
|
|
|
|
|
system.cpu.ipc 0.354427 # IPC: instructions per cycle
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked
|
|
|
|
|
system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped
|
|
|
|
|
system.cpu.dcache.tags.replacements 842581 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks.
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 41631817 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1209932 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 698329 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.icache.tags.replacements 2897467 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.icache.tags.tag_accesses 60477795 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 60477795 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 54681814 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 54681814 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 54681814 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 54681814 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 54681814 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 54681814 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 2897991 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 2897991 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 2897991 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 2897991 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 2897991 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 2897991 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39294300362 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 39294300362 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 39294300362 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 39294300362 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 39294300362 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 39294300362 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 57579805 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 57579805 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 57579805 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 57579805 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 57579805 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 57579805 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050330 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.050330 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.050330 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.050330 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.050330 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.050330 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.151965 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13559.151965 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 13559.151965 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 13559.151965 # average overall miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897991 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 2897991 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 2897991 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 2897991 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 2897991 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 2897991 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34937740638 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 34937740638 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34937740638 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 34937740638 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34937740638 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 34937740638 # number of overall MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050330 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.050330 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.050330 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.848565 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.848565 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.replacements 96766 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 65065.875064 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 4045925 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 162028 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 24.970530 # Average number of references to valid blocks.
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 47500.722639 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.826977 # Average occupied blocks per requestor
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12189.076144 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 5308.248921 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.724804 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001035 # Average percentage of cache occupancy
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185991 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.080997 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.992826 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2302 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6937 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55861 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.tags.tag_accesses 36601578 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 36601578 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70583 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4448 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2875013 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 532926 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 3482970 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 698329 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 698329 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 164703 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 164703 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 70583 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 4448 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2875013 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 697629 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 3647673 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 70583 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 4448 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2875013 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 697629 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 3647673 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 121 # number of ReadReq misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 22948 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 14295 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 37365 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2778 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2778 # number of UpgradeReq misses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 131196 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 131196 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 121 # number of demand (read+write) misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 22948 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 145491 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 168561 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 121 # number of overall misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 22948 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 145491 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 168561 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10389500 # number of ReadReq miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838002000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1203040290 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3051514290 # number of ReadReq miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10205321187 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10205321187 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10389500 # number of demand (read+write) miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1838002000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11408361477 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 13256835477 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10389500 # number of overall miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1838002000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11408361477 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 13256835477 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70704 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4449 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897961 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 547221 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 3520335 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 698329 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 698329 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2831 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2831 # number of UpgradeReq accesses(hits+misses)
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 295899 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 295899 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70704 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 4449 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 2897961 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 843120 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 3816234 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70704 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 4449 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 2897961 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 843120 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 3816234 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001711 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000225 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007919 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026123 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.010614 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981279 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981279 # miss rate for UpgradeReq accesses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443381 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.443381 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001711 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000225 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007919 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.172563 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.044169 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001711 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000225 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007919 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.172563 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.044169 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85863.636364 # average ReadReq miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80094.213003 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84158.117524 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81667.718185 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.435925 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.435925 # average UpgradeReq miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77786.831817 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77786.831817 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 78647.109812 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 78647.109812 # average overall miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 88357 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 88357 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 143 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 161 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 121 # number of ReadReq MSHR misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22930 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14152 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 37204 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2778 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2778 # number of UpgradeReq MSHR misses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131196 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 131196 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 121 # number of demand (read+write) MSHR misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 22930 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 145348 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 168400 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 121 # number of overall MSHR misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 22930 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 145348 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 168400 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8873000 # number of ReadReq MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1549821750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1015754460 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574519210 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49350278 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49350278 # number of UpgradeReq MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8563537813 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8563537813 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8873000 # number of demand (read+write) MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1549821750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9579292273 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11138057023 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8873000 # number of overall MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1549821750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9579292273 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11138057023 # number of overall MSHR miss cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400289500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592019250 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151564500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151564500 # number of WriteReq MSHR uncacheable cycles
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551854000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743583750 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025862 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010568 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981279 # mshr miss rate for UpgradeReq accesses
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443381 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443381 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.044127 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.044127 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average ReadReq mshr miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67589.260794 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71774.622668 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69200.064778 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17764.678906 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17764.678906 # average UpgradeReq mshr miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65272.857503 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65272.857503 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
2015-01-04 20:02:12 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2833 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 295899 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 295899 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802295 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2507794 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15026 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159855 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 61238 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use
|
2014-07-28 07:48:21 +02:00
|
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
|
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::realview.ide 234 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 234 # number of overall misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked
|
2014-07-23 23:09:05 +02:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked
|
2014-07-28 07:48:21 +02:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked
|
2014-07-28 07:48:21 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
2014-07-28 07:48:21 +02:00
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
|
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
2014-12-02 12:08:25 +01:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
2014-10-30 05:18:29 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2015-03-19 13:41:32 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.trans_dist::ReadReq 71736 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 71736 # Transaction distribution
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.trans_dist::WriteReq 27583 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 27583 # Transaction distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.trans_dist::Writeback 124547 # Transaction distribution
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 129383 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 129383 # Transaction distribution
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes)
|
2014-12-02 12:08:25 +01:00
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes)
|
2014-12-02 12:08:25 +01:00
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 505 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 332236 # Request fanout histogram
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.snoop_fanout::total 332236 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2015-03-19 13:41:32 +01:00
|
|
|
system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks)
|
2014-11-12 15:05:25 +01:00
|
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
|
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
|
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
|
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
|
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
2014-07-23 23:09:05 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
