2011-08-19 22:08:09 +02:00
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---------- Begin Simulation Statistics ----------
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2013-01-08 14:54:16 +01:00
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sim_seconds 1.092969 # Number of seconds simulated
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sim_ticks 1092968826500 # Number of ticks simulated
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final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-08-19 22:08:09 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2013-01-08 14:54:16 +01:00
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host_inst_rate 64747 # Simulator instruction rate (inst/s)
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host_op_rate 83356 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1148881552 # Simulator tick rate (ticks/s)
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host_mem_usage 415112 # Number of bytes of host memory used
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host_seconds 951.33 # Real time elapsed on the host
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sim_insts 61595972 # Number of instructions simulated
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sim_ops 79298956 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 59 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 351 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 410 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 59 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 351 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 410 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 59 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 351 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 410 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 408768 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4356148 # Number of bytes read from this memory
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2013-01-07 19:05:54 +01:00
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system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
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2013-01-08 14:54:16 +01:00
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system.physmem.bytes_read::cpu1.inst 407360 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 5254000 # Number of bytes read from this memory
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system.physmem.bytes_read::total 59186980 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 408768 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 407360 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 816128 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4265536 # Number of bytes written to this memory
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2012-09-25 18:49:41 +02:00
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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2013-01-08 14:54:16 +01:00
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system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7292880 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 6387 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 68137 # Number of read requests responded to by this memory
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2013-01-07 19:05:54 +01:00
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system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
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2013-01-08 14:54:16 +01:00
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system.physmem.num_reads::cpu1.inst 6365 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6257887 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66649 # Number of write requests responded to by this memory
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2012-09-25 18:49:41 +02:00
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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2013-01-08 14:54:16 +01:00
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system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 823485 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 44611322 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 644 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 117 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 373998 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3985610 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 995 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 372710 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 4807090 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 54152487 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 373998 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 372710 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 746707 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3902706 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 15554 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 2754282 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6672542 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3902706 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 44611322 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 644 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 117 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 373998 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 4001164 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 995 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 372710 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 7561372 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 60825028 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 6257887 # Total number of read requests seen
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system.physmem.writeReqs 823485 # Total number of write requests seen
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system.physmem.cpureqs 281561 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 400504768 # Total number of bytes read from memory
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system.physmem.bytesWritten 52703040 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 59186980 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7292880 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 99 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 12576 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 391078 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 391463 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 391295 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 391282 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 391106 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 390838 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 390638 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 390722 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 391599 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 391075 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 391119 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 391349 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 391010 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 391200 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 391075 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 390939 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50710 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 51048 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50959 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 50974 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 51767 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 51577 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 51386 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 51435 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51989 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51698 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 51575 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51742 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51637 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 51658 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51582 # Track writes on a per bank basis
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2012-10-25 19:14:42 +02:00
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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2013-01-08 14:54:16 +01:00
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system.physmem.numWrRetry 1176096 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1092967540000 # Total gap between requests
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 105 # Categorize read packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.readPktSize::6 162934 # Categorize read packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.writePktSize::2 1932932 # categorize write packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.writePktSize::6 66649 # categorize write packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.neitherpktsize::6 12576 # categorize neither packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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2013-01-08 14:54:16 +01:00
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system.physmem.rdQLenPdf::0 496879 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 431716 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 387410 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 401103 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1104120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1111115 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2162095 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 27972 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 13923 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 13366 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 13210 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 24040 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 20771 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 31247 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 16482 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2056 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 191 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 73 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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2013-01-08 14:54:16 +01:00
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system.physmem.wrQLenPdf::0 3123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 3366 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3475 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::4 3601 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::5 3806 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::6 3971 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::7 4155 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::8 4342 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::9 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::10 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::11 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::12 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::13 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::14 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::15 35804 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::16 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 35803 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::23 32681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 32541 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 32438 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 32329 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 32203 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 31998 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 31833 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 31649 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 31462 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2013-01-08 14:54:16 +01:00
|
|
|
system.physmem.totQLat 164150101325 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 197462743325 # Sum of mem lat for all requests
|
|
|
|
|
system.physmem.totBusLat 25031152000 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 8281490000 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat 26231.33 # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat 1323.39 # Average bank access latency per request
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
2013-01-08 14:54:16 +01:00
|
|
|
system.physmem.avgMemAccLat 31554.72 # Average memory access latency
|
|
|
|
|
system.physmem.avgRdBW 366.44 # Average achieved read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgWrBW 48.22 # Average achieved write bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedRdBW 54.15 # Average consumed read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedWrBW 6.67 # Average consumed write bandwidth in MB/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
2013-01-08 14:54:16 +01:00
|
|
|
system.physmem.busUtil 2.59 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 0.18 # Average read queue length over time
|
|
|
|
|
system.physmem.avgWrQLen 9.65 # Average write queue length over time
|
|
|
|
|
system.physmem.readRowHits 6229568 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 789194 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 99.55 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 95.84 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 154344.04 # Average gap between requests
|
|
|
|
|
system.l2c.replacements 72641 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 53795.283774 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1870380 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 137779 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.avg_refs 13.575218 # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.occ_blocks::writebacks 39404.658188 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.dtb.walker 3.902854 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.000810 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.inst 4010.788267 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.data 2816.355225 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.dtb.walker 10.914137 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.inst 3736.677098 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.data 3811.987195 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_percent::writebacks 0.601267 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
|
2012-11-02 17:50:06 +01:00
|
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.occ_percent::cpu0.inst 0.061200 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.data 0.042974 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000167 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.inst 0.057017 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.data 0.058166 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::total 0.820851 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 31008 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 4497 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.inst 386125 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.data 166511 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 49385 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 5433 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.inst 590760 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.data 198089 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1431808 # number of ReadReq hits
|
|
|
|
|
system.l2c.Writeback_hits::writebacks 581288 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 581288 # number of Writeback hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1275 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu1.data 889 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 2164 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 334 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu0.data 48752 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu1.data 58366 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 107118 # number of ReadExReq hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.dtb.walker 31008 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.itb.walker 4497 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.inst 386125 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.data 215263 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.dtb.walker 49385 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.itb.walker 5433 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.inst 590760 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.data 256455 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 1538926 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.dtb.walker 31008 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.itb.walker 4497 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.inst 386125 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.data 215263 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.dtb.walker 49385 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.itb.walker 5433 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.inst 590760 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.data 256455 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 1538926 # number of overall hits
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.inst 6267 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.data 6396 # number of ReadReq misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.ReadReq_misses::cpu1.inst 6329 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.data 6335 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 25357 # number of ReadReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu0.data 5149 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3784 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 8933 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 643 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::total 1051 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu0.data 63102 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu1.data 76972 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 140074 # number of ReadExReq misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.inst 6267 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.data 69498 # number of demand (read+write) misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.demand_misses::cpu1.inst 6329 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu1.data 83307 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 165431 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.inst 6267 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.data 69498 # number of overall misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.overall_misses::cpu1.inst 6329 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu1.data 83307 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 165431 # number of overall misses
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 717000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 326644000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 351867998 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1444500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 345049500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 365249000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::total 1391089998 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 9054984 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 11616000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::total 20670984 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 661000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846498 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::total 3507498 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3082603488 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 4220265994 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::total 7302869482 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 717000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.inst 326644000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.data 3434471486 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 1444500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.inst 345049500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.data 4585514994 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::total 8693959480 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 717000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.inst 326644000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.data 3434471486 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 1444500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.inst 345049500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.data 4585514994 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::total 8693959480 # number of overall miss cycles
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 31019 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 4499 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.inst 392392 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.data 172907 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 49402 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 5433 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.inst 597089 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.data 204424 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 1457165 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::writebacks 581288 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 581288 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 6424 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4673 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 11097 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 832 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 553 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 1385 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu0.data 111854 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu1.data 135338 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 247192 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 31019 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.itb.walker 4499 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.inst 392392 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.data 284761 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 49402 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.itb.walker 5433 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.inst 597089 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.data 339762 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 1704357 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 31019 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.itb.walker 4499 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.inst 392392 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.data 284761 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 49402 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.itb.walker 5433 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.inst 597089 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.data 339762 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 1704357 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000445 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015971 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.036991 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010600 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.030990 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.017402 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801526 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809758 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::total 0.804992 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772837 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737794 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.758845 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.564146 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.568739 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 0.566661 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000445 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015971 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.data 0.244057 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.010600 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.data 0.245192 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.097064 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000445 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015971 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.data 0.244057 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.010600 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.data 0.245192 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.097064 # miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52121.270145 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 55013.758286 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54518.802338 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 57655.722178 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 54860.196317 # average ReadReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1758.590794 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3069.767442 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 2314.002463 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1027.993779 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6976.710784 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 3337.295909 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 48851.121803 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54828.586941 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52135.795951 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52121.270145 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 49418.278022 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 54518.802338 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 55043.573697 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 52553.387696 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52121.270145 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 49418.278022 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 54518.802338 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 55043.573697 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 52553.387696 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.writebacks::writebacks 66649 # number of writebacks
|
|
|
|
|
system.l2c.writebacks::total 66649 # number of writebacks
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 6263 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 6358 # number of ReadReq MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 6322 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 6312 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::total 25285 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5149 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3784 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::total 8933 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 643 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 408 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1051 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 63102 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 76972 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::total 140074 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu0.inst 6263 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu0.data 69460 # number of demand (read+write) MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.inst 6322 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu1.data 83284 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::total 165359 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu0.inst 6263 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu0.data 69460 # number of overall MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.inst 6322 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu1.data 83284 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::total 165359 # number of overall MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 578020 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 247369568 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 268980439 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 264820900 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 284075297 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1067144258 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51815000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38464202 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 90279202 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474121 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4094402 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10568523 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2301961811 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3263562835 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 5565524646 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 578020 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 247369568 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2570942250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 264820900 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 3547638132 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::total 6632668904 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 578020 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 247369568 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2570942250 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 264820900 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 3547638132 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::total 6632668904 # number of overall MSHR miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12397759064 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154673182999 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 167077315290 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 998522739 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17312425061 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 18310947800 # number of WriteReq MSHR uncacheable cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles
|
2013-01-08 14:54:16 +01:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13396281803 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171985608060 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::total 185388263090 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036771 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030877 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.017352 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801526 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809758 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.804992 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772837 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737794 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758845 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.564146 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568739 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.566661 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 0.097021 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 0.097021 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42305.825574 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45005.592047 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 42204.637453 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10063.119052 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10164.958245 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.257920 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.617418 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.299020 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10055.683159 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36480.013486 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42399.350868 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 39732.745877 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
|
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
|
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dtb.read_hits 8918270 # DTB read hits
|
|
|
|
|
system.cpu0.dtb.read_misses 33761 # DTB read misses
|
|
|
|
|
system.cpu0.dtb.write_hits 5143475 # DTB write hits
|
|
|
|
|
system.cpu0.dtb.write_misses 6030 # DTB write misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dtb.flush_entries 2137 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu0.dtb.align_faults 1055 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu0.dtb.prefetch_faults 365 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dtb.perms_faults 538 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu0.dtb.read_accesses 8952031 # DTB read accesses
|
|
|
|
|
system.cpu0.dtb.write_accesses 5149505 # DTB write accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dtb.hits 14061745 # DTB hits
|
|
|
|
|
system.cpu0.dtb.misses 39791 # DTB misses
|
|
|
|
|
system.cpu0.dtb.accesses 14101536 # DTB accesses
|
|
|
|
|
system.cpu0.itb.inst_hits 4226389 # ITB inst hits
|
|
|
|
|
system.cpu0.itb.inst_misses 5148 # ITB inst misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.itb.flush_entries 1370 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.itb.inst_accesses 4231537 # ITB inst accesses
|
|
|
|
|
system.cpu0.itb.hits 4226389 # DTB hits
|
|
|
|
|
system.cpu0.itb.misses 5148 # DTB misses
|
|
|
|
|
system.cpu0.itb.accesses 4231537 # DTB accesses
|
|
|
|
|
system.cpu0.numCycles 67785734 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.BPredUnit.lookups 6012491 # Number of BP lookups
|
|
|
|
|
system.cpu0.BPredUnit.condPredicted 4585363 # Number of conditional branches predicted
|
|
|
|
|
system.cpu0.BPredUnit.condIncorrect 296577 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu0.BPredUnit.BTBLookups 3765620 # Number of BTB lookups
|
|
|
|
|
system.cpu0.BPredUnit.BTBHits 2919015 # Number of BTB hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.BPredUnit.usedRAS 674578 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu0.BPredUnit.RASInCorrect 28863 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu0.fetch.predictedBranches 3593593 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu0.fetch.Cycles 7526717 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu0.fetch.SquashCycles 1460555 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu0.fetch.TlbCycles 62547 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu0.fetch.BlockedCycles 20715231 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu0.fetch.MiscStallCycles 4834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu0.fetch.PendingTrapStallCycles 54522 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 85492 # Number of stall cycles due to pending quiesce instructions
|
|
|
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu0.fetch.CacheLines 4224665 # Number of cache lines fetched
|
|
|
|
|
system.cpu0.fetch.IcacheSquashes 156872 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu0.fetch.ItlbSquashes 2292 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu0.fetch.rateDist::samples 41263116 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::mean 1.003783 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::stdev 2.384047 # Number of instructions fetched each cycle (Total)
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.fetch.rateDist::0 33743827 81.78% 81.78% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::1 566856 1.37% 83.15% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::2 818944 1.98% 85.14% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::3 676218 1.64% 86.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::4 773991 1.88% 88.65% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::5 560705 1.36% 90.01% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::6 670652 1.63% 91.63% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::7 352961 0.86% 92.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::8 3098962 7.51% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.fetch.rateDist::total 41263116 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.branchRate 0.088698 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu0.fetch.rate 0.472813 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu0.decode.IdleCycles 12272697 # Number of cycles decode is idle
|
|
|
|
|
system.cpu0.decode.BlockedCycles 20662299 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu0.decode.RunCycles 6831890 # Number of cycles decode is running
|
|
|
|
|
system.cpu0.decode.UnblockCycles 510283 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu0.decode.SquashCycles 985947 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu0.decode.BranchResolved 936613 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu0.decode.BranchMispred 64715 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu0.decode.DecodedInsts 40060631 # Number of instructions handled by decode
|
|
|
|
|
system.cpu0.decode.SquashedInsts 213244 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu0.rename.SquashCycles 985947 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu0.rename.IdleCycles 12836550 # Number of cycles rename is idle
|
|
|
|
|
system.cpu0.rename.BlockCycles 5831447 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu0.rename.serializeStallCycles 12738222 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu0.rename.RunCycles 6726939 # Number of cycles rename is running
|
|
|
|
|
system.cpu0.rename.UnblockCycles 2144011 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu0.rename.RenamedInsts 38954643 # Number of instructions processed by rename
|
|
|
|
|
system.cpu0.rename.ROBFullEvents 2110 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu0.rename.IQFullEvents 419770 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu0.rename.LSQFullEvents 1235917 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers
|
|
|
|
|
system.cpu0.rename.RenamedOperands 39310777 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu0.rename.RenameLookups 175935751 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu0.rename.int_rename_lookups 175901847 # Number of integer rename lookups
|
|
|
|
|
system.cpu0.rename.fp_rename_lookups 33904 # Number of floating rename lookups
|
|
|
|
|
system.cpu0.rename.CommittedMaps 30931608 # Number of HB maps that are committed
|
|
|
|
|
system.cpu0.rename.UndoneMaps 8379168 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu0.rename.serializingInsts 411632 # count of serializing insts renamed
|
|
|
|
|
system.cpu0.rename.tempSerializingInsts 370766 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu0.rename.skidInsts 5325827 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu0.memDep0.insertedLoads 7663556 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu0.memDep0.insertedStores 5690026 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu0.memDep0.conflictingLoads 1120184 # Number of conflicting loads.
|
|
|
|
|
system.cpu0.memDep0.conflictingStores 1252239 # Number of conflicting stores.
|
|
|
|
|
system.cpu0.iq.iqInstsAdded 36870649 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu0.iq.iqNonSpecInstsAdded 896350 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu0.iq.iqInstsIssued 37273811 # Number of instructions issued
|
|
|
|
|
system.cpu0.iq.iqSquashedInstsIssued 81085 # Number of squashed instructions issued
|
|
|
|
|
system.cpu0.iq.iqSquashedInstsExamined 6313763 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu0.iq.iqSquashedOperandsExamined 13211798 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 257333 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::samples 41263116 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::mean 0.903320 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.511259 # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iq.issued_per_cycle::0 26116346 63.29% 63.29% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::1 5727985 13.88% 77.17% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::2 3164328 7.67% 84.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::3 2471717 5.99% 90.83% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::4 2127646 5.16% 95.99% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::5 929575 2.25% 98.24% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::6 487199 1.18% 99.42% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::7 186194 0.45% 99.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::8 52126 0.13% 100.00% # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iq.issued_per_cycle::total 41263116 # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iq.fu_full::IntAlu 25847 2.42% 2.42% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::IntMult 453 0.04% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::MemRead 842941 78.82% 81.28% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::MemWrite 200262 18.72% 100.00% # attempts to use FU when none available
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iq.FU_type_0::No_OpClass 52409 0.14% 0.14% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::IntAlu 22347449 59.95% 60.10% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::IntMult 46908 0.13% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::MemRead 9376305 25.16% 85.38% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::MemWrite 5450017 14.62% 100.00% # Type of FU issued
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iq.FU_type_0::total 37273811 # Type of FU issued
|
|
|
|
|
system.cpu0.iq.rate 0.549877 # Inst issue rate
|
|
|
|
|
system.cpu0.iq.fu_busy_cnt 1069503 # FU busy when requested
|
|
|
|
|
system.cpu0.iq.fu_busy_rate 0.028693 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu0.iq.int_inst_queue_reads 116992528 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu0.iq.int_inst_queue_writes 44088817 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 34369527 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_reads 8360 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3860 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu0.iq.int_alu_accesses 38286519 # Number of integer alu accesses
|
|
|
|
|
system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses
|
|
|
|
|
system.cpu0.iew.lsq.thread0.forwLoads 307254 # Number of loads that had data forwarded from stores
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1385688 # Number of loads squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 2397 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 13227 # Number of memory ordering violations
|
|
|
|
|
system.cpu0.iew.lsq.thread0.squashedStores 538655 # Number of stores squashed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 2192760 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 5477 # Number of times an access to memory failed due to the cache being blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iew.iewSquashCycles 985947 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu0.iew.iewBlockCycles 4198442 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu0.iew.iewUnblockCycles 101973 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu0.iew.iewDispatchedInsts 37885007 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu0.iew.iewDispSquashedInsts 86572 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu0.iew.iewDispLoadInsts 7663556 # Number of dispatched load instructions
|
|
|
|
|
system.cpu0.iew.iewDispStoreInsts 5690026 # Number of dispatched store instructions
|
|
|
|
|
system.cpu0.iew.iewDispNonSpecInsts 571892 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu0.iew.iewIQFullEvents 40888 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu0.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu0.iew.memOrderViolationEvents 13227 # Number of memory order violations
|
|
|
|
|
system.cpu0.iew.predictedTakenIncorrect 150955 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu0.iew.predictedNotTakenIncorrect 118096 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu0.iew.branchMispredicts 269051 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu0.iew.iewExecutedInsts 36896358 # Number of executed instructions
|
|
|
|
|
system.cpu0.iew.iewExecLoadInsts 9233299 # Number of load instructions executed
|
|
|
|
|
system.cpu0.iew.iewExecSquashedInsts 377453 # Number of squashed instructions skipped in execute
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iew.exec_nop 118008 # number of nop insts executed
|
|
|
|
|
system.cpu0.iew.exec_refs 14636338 # number of memory reference insts executed
|
|
|
|
|
system.cpu0.iew.exec_branches 4860481 # Number of branches executed
|
|
|
|
|
system.cpu0.iew.exec_stores 5403039 # Number of stores executed
|
|
|
|
|
system.cpu0.iew.exec_rate 0.544309 # Inst execution rate
|
|
|
|
|
system.cpu0.iew.wb_sent 36702505 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu0.iew.wb_count 34373387 # cumulative count of insts written-back
|
|
|
|
|
system.cpu0.iew.wb_producers 18311880 # num instructions producing a value
|
|
|
|
|
system.cpu0.iew.wb_consumers 35235348 # num instructions consuming a value
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.iew.wb_rate 0.507089 # insts written-back per cycle
|
|
|
|
|
system.cpu0.iew.wb_fanout 0.519702 # average fanout of values written-back
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.commit.commitSquashedInsts 6136748 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu0.commit.commitNonSpecStalls 639017 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu0.commit.branchMispredicts 232971 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::samples 40277169 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::mean 0.776860 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.743491 # Number of insts commited each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.commit.committed_per_cycle::0 28628964 71.08% 71.08% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::1 5718437 14.20% 85.28% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::2 1895078 4.71% 89.98% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::3 977858 2.43% 92.41% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::4 774389 1.92% 94.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::5 507385 1.26% 95.59% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::6 386799 0.96% 96.55% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::7 213802 0.53% 97.08% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::8 1174457 2.92% 100.00% # Number of insts commited each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.commit.committed_per_cycle::total 40277169 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committedInsts 23678178 # Number of instructions committed
|
|
|
|
|
system.cpu0.commit.committedOps 31289712 # Number of ops (including micro ops) committed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.commit.refs 11429239 # Number of memory references committed
|
|
|
|
|
system.cpu0.commit.loads 6277868 # Number of loads committed
|
|
|
|
|
system.cpu0.commit.membars 229666 # Number of memory barriers committed
|
|
|
|
|
system.cpu0.commit.branches 4244753 # Number of branches committed
|
2012-09-25 18:49:41 +02:00
|
|
|
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.commit.int_insts 27646281 # Number of committed integer instructions.
|
|
|
|
|
system.cpu0.commit.function_calls 489273 # Number of function calls committed.
|
|
|
|
|
system.cpu0.commit.bw_lim_events 1174457 # number cycles where commit BW limit reached
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.rob.rob_reads 75678018 # The number of ROB reads
|
|
|
|
|
system.cpu0.rob.rob_writes 75840987 # The number of ROB writes
|
|
|
|
|
system.cpu0.timesIdled 360810 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu0.idleCycles 26522618 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu0.quiesceCycles 2118110205 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
|
|
|
system.cpu0.committedInsts 23597436 # Number of Instructions Simulated
|
|
|
|
|
system.cpu0.committedOps 31208970 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu0.committedInsts_total 23597436 # Number of Instructions Simulated
|
|
|
|
|
system.cpu0.cpi 2.872589 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu0.cpi_total 2.872589 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu0.ipc 0.348118 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu0.ipc_total 0.348118 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu0.int_regfile_reads 172012852 # number of integer regfile reads
|
|
|
|
|
system.cpu0.int_regfile_writes 34120799 # number of integer regfile writes
|
|
|
|
|
system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads
|
|
|
|
|
system.cpu0.fp_regfile_writes 892 # number of floating regfile writes
|
|
|
|
|
system.cpu0.misc_regfile_reads 13056447 # number of misc regfile reads
|
|
|
|
|
system.cpu0.misc_regfile_writes 451188 # number of misc regfile writes
|
|
|
|
|
system.cpu0.icache.replacements 392549 # number of replacements
|
|
|
|
|
system.cpu0.icache.tagsinuse 511.079018 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.icache.total_refs 3800627 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.sampled_refs 393061 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.avg_refs 9.669306 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.warmup_cycle 6496390000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 511.079018 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.998201 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.occ_percent::total 0.998201 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 3800627 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::total 3800627 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.demand_hits::cpu0.inst 3800627 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.demand_hits::total 3800627 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.overall_hits::cpu0.inst 3800627 # number of overall hits
|
|
|
|
|
system.cpu0.icache.overall_hits::total 3800627 # number of overall hits
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 423907 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::total 423907 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.demand_misses::cpu0.inst 423907 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.demand_misses::total 423907 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.overall_misses::cpu0.inst 423907 # number of overall misses
|
|
|
|
|
system.cpu0.icache.overall_misses::total 423907 # number of overall misses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5778558992 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5778558992 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5778558992 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::total 5778558992 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5778558992 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::total 5778558992 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4224534 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::total 4224534 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 4224534 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.demand_accesses::total 4224534 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 4224534 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::total 4224534 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100344 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.100344 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100344 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::total 0.100344 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100344 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::total 0.100344 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13631.666833 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13631.666833 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13631.666833 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13631.666833 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 3110 # number of cycles access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.326797 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30826 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 30826 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 30826 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.icache.demand_mshr_hits::total 30826 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 30826 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.icache.overall_mshr_hits::total 30826 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393081 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 393081 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 393081 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::total 393081 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 393081 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::total 393081 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4722265492 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4722265492 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4722265492 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4722265492 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4722265492 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4722265492 # number of overall MSHR miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093047 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.093047 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.093047 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12013.466670 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dcache.replacements 276186 # number of replacements
|
|
|
|
|
system.cpu0.dcache.tagsinuse 460.207954 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 9271152 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.sampled_refs 276698 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.avg_refs 33.506393 # Average number of references to valid blocks.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 460.207954 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.898844 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.occ_percent::total 0.898844 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5791916 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::total 5791916 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3159128 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::total 3159128 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139197 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 139197 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137104 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::total 137104 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::cpu0.data 8951044 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::total 8951044 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::cpu0.data 8951044 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::total 8951044 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 391497 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::total 391497 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1585211 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::total 1585211 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8805 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 8805 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7503 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7503 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1976708 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::total 1976708 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1976708 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::total 1976708 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5419802000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5419802000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59847292371 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 59847292371 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88405500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 88405500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46738000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 46738000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 65267094371 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::total 65267094371 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 65267094371 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::total 65267094371 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6183413 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::total 6183413 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744339 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::total 4744339 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144607 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 144607 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 10927752 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.demand_accesses::total 10927752 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 10927752 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::total 10927752 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063314 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.063314 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334127 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.334127 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059492 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059492 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051885 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051885 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180889 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::total 0.180889 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180889 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::total 0.180889 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13843.789352 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13843.789352 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37753.518220 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 37753.518220 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10040.374787 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10040.374787 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6229.241637 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6229.241637 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 33018.075695 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 33018.075695 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 8715 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_targets 3535 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_mshrs 594 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.671717 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 42.590361 # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.dcache.writebacks::writebacks 256562 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.writebacks::total 256562 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202833 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 202833 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454685 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1454685 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 458 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 458 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657518 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.dcache.demand_mshr_hits::total 1657518 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657518 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.dcache.overall_mshr_hits::total 1657518 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188664 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 188664 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130526 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 130526 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8347 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8347 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7503 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7503 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 319190 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses::total 319190 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 319190 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::total 319190 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355812500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2355812500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3979098490 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3979098490 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66495500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66495500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31732000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31732000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6334910990 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 6334910990 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6334910990 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 6334910990 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504511500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504511500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128583377 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128583377 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14633094877 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14633094877 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030511 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030511 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027512 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027512 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056398 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056398 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051885 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051885 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12486.815185 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12486.815185 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30485.102508 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30485.102508 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7966.395112 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7966.395112 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4229.241637 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4229.241637 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dtb.read_hits 42721233 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 41267 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_hits 6827437 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 11457 # DTB write misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu1.dtb.align_faults 2630 # Number of TLB faults due to alignment restrictions
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu1.dtb.read_accesses 42762500 # DTB read accesses
|
|
|
|
|
system.cpu1.dtb.write_accesses 6838894 # DTB write accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dtb.hits 49548670 # DTB hits
|
|
|
|
|
system.cpu1.dtb.misses 52724 # DTB misses
|
|
|
|
|
system.cpu1.dtb.accesses 49601394 # DTB accesses
|
|
|
|
|
system.cpu1.itb.inst_hits 7583980 # ITB inst hits
|
|
|
|
|
system.cpu1.itb.inst_misses 5601 # ITB inst misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.itb.flush_entries 1561 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.itb.perms_faults 1591 # Number of TLB faults due to permissions restrictions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.itb.inst_accesses 7589581 # ITB inst accesses
|
|
|
|
|
system.cpu1.itb.hits 7583980 # DTB hits
|
|
|
|
|
system.cpu1.itb.misses 5601 # DTB misses
|
|
|
|
|
system.cpu1.itb.accesses 7589581 # DTB accesses
|
|
|
|
|
system.cpu1.numCycles 406854445 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.BPredUnit.lookups 8781590 # Number of BP lookups
|
|
|
|
|
system.cpu1.BPredUnit.condPredicted 7165099 # Number of conditional branches predicted
|
|
|
|
|
system.cpu1.BPredUnit.condIncorrect 410272 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu1.BPredUnit.BTBLookups 5784510 # Number of BTB lookups
|
|
|
|
|
system.cpu1.BPredUnit.BTBHits 4949628 # Number of BTB hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.BPredUnit.usedRAS 773605 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu1.BPredUnit.RASInCorrect 42847 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu1.fetch.predictedBranches 5723233 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu1.fetch.Cycles 13164545 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu1.fetch.SquashCycles 3370379 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu1.fetch.TlbCycles 67214 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu1.fetch.BlockedCycles 77426772 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu1.fetch.MiscStallCycles 4687 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu1.fetch.PendingTrapStallCycles 46358 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 129737 # Number of stall cycles due to pending quiesce instructions
|
|
|
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 707 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu1.fetch.CacheLines 7581976 # Number of cache lines fetched
|
|
|
|
|
system.cpu1.fetch.IcacheSquashes 531329 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu1.fetch.ItlbSquashes 3060 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu1.fetch.rateDist::samples 112134243 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::mean 0.659620 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::stdev 1.988948 # Number of instructions fetched each cycle (Total)
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.fetch.rateDist::0 98977030 88.27% 88.27% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::1 796888 0.71% 88.98% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::2 939707 0.84% 89.82% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::3 1694875 1.51% 91.33% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::4 1403619 1.25% 92.58% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::5 573280 0.51% 93.09% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::6 1928107 1.72% 94.81% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::7 410374 0.37% 95.18% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::8 5410363 4.82% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.fetch.rateDist::total 112134243 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.branchRate 0.021584 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu1.fetch.rate 0.148737 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu1.decode.IdleCycles 20329334 # Number of cycles decode is idle
|
|
|
|
|
system.cpu1.decode.BlockedCycles 77067438 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu1.decode.RunCycles 11999240 # Number of cycles decode is running
|
|
|
|
|
system.cpu1.decode.UnblockCycles 528326 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu1.decode.SquashCycles 2209905 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu1.decode.BranchResolved 1105816 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu1.decode.BranchMispred 98089 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu1.decode.DecodedInsts 69983071 # Number of instructions handled by decode
|
|
|
|
|
system.cpu1.decode.SquashedInsts 327113 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu1.rename.SquashCycles 2209905 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu1.rename.IdleCycles 21512186 # Number of cycles rename is idle
|
|
|
|
|
system.cpu1.rename.BlockCycles 32033439 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu1.rename.serializeStallCycles 40715711 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu1.rename.RunCycles 11249430 # Number of cycles rename is running
|
|
|
|
|
system.cpu1.rename.UnblockCycles 4413572 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu1.rename.RenamedInsts 66189803 # Number of instructions processed by rename
|
|
|
|
|
system.cpu1.rename.ROBFullEvents 19593 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu1.rename.IQFullEvents 681290 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu1.rename.LSQFullEvents 3157378 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu1.rename.FullRegisterEvents 32035 # Number of times there has been no free registers
|
|
|
|
|
system.cpu1.rename.RenamedOperands 69538015 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu1.rename.RenameLookups 303909752 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu1.rename.int_rename_lookups 303850528 # Number of integer rename lookups
|
|
|
|
|
system.cpu1.rename.fp_rename_lookups 59224 # Number of floating rename lookups
|
|
|
|
|
system.cpu1.rename.CommittedMaps 49060717 # Number of HB maps that are committed
|
|
|
|
|
system.cpu1.rename.UndoneMaps 20477298 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu1.rename.serializingInsts 445152 # count of serializing insts renamed
|
|
|
|
|
system.cpu1.rename.tempSerializingInsts 388313 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu1.rename.skidInsts 7961235 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu1.memDep0.insertedLoads 12608499 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu1.memDep0.insertedStores 7947542 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu1.memDep0.conflictingLoads 1037744 # Number of conflicting loads.
|
|
|
|
|
system.cpu1.memDep0.conflictingStores 1535939 # Number of conflicting stores.
|
|
|
|
|
system.cpu1.iq.iqInstsAdded 60784720 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1155099 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu1.iq.iqInstsIssued 87803920 # Number of instructions issued
|
|
|
|
|
system.cpu1.iq.iqSquashedInstsIssued 97322 # Number of squashed instructions issued
|
|
|
|
|
system.cpu1.iq.iqSquashedInstsExamined 13491429 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu1.iq.iqSquashedOperandsExamined 36062520 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 274254 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::samples 112134243 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::mean 0.783025 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.519999 # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iq.issued_per_cycle::0 82080142 73.20% 73.20% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::1 8453890 7.54% 80.74% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::2 4228870 3.77% 84.51% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::3 3673146 3.28% 87.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::4 10396618 9.27% 97.06% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::5 1923791 1.72% 98.77% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::6 1051838 0.94% 99.71% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::7 251187 0.22% 99.93% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::8 74761 0.07% 100.00% # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iq.issued_per_cycle::total 112134243 # Number of insts issued each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iq.fu_full::IntAlu 29715 0.38% 0.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::MemRead 7547628 96.04% 96.43% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::MemWrite 280810 3.57% 100.00% # attempts to use FU when none available
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntAlu 36673483 41.77% 42.13% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntMult 59172 0.07% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1514 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::MemRead 43579800 49.63% 91.83% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::MemWrite 7175925 8.17% 100.00% # Type of FU issued
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iq.FU_type_0::total 87803920 # Type of FU issued
|
|
|
|
|
system.cpu1.iq.rate 0.215812 # Inst issue rate
|
|
|
|
|
system.cpu1.iq.fu_busy_cnt 7859149 # FU busy when requested
|
|
|
|
|
system.cpu1.iq.fu_busy_rate 0.089508 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu1.iq.int_inst_queue_reads 295735701 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu1.iq.int_inst_queue_writes 75439999 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 53226631 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_reads 15376 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_writes 8066 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6868 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.int_alu_accesses 95340871 # Number of integer alu accesses
|
|
|
|
|
system.cpu1.iq.fp_alu_accesses 8201 # Number of floating point alu accesses
|
|
|
|
|
system.cpu1.iew.lsq.thread0.forwLoads 343143 # Number of loads that had data forwarded from stores
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2852269 # Number of loads squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3976 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 17384 # Number of memory ordering violations
|
|
|
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1106708 # Number of stores squashed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 31919671 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 693087 # Number of times an access to memory failed due to the cache being blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iew.iewSquashCycles 2209905 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu1.iew.iewBlockCycles 24121244 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu1.iew.iewUnblockCycles 365124 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu1.iew.iewDispatchedInsts 62044608 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu1.iew.iewDispSquashedInsts 111941 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu1.iew.iewDispLoadInsts 12608499 # Number of dispatched load instructions
|
|
|
|
|
system.cpu1.iew.iewDispStoreInsts 7947542 # Number of dispatched store instructions
|
|
|
|
|
system.cpu1.iew.iewDispNonSpecInsts 865588 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu1.iew.iewIQFullEvents 68372 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu1.iew.iewLSQFullEvents 3578 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu1.iew.memOrderViolationEvents 17384 # Number of memory order violations
|
|
|
|
|
system.cpu1.iew.predictedTakenIncorrect 203207 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu1.iew.predictedNotTakenIncorrect 155936 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu1.iew.branchMispredicts 359143 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu1.iew.iewExecutedInsts 86098386 # Number of executed instructions
|
|
|
|
|
system.cpu1.iew.iewExecLoadInsts 43091016 # Number of load instructions executed
|
|
|
|
|
system.cpu1.iew.iewExecSquashedInsts 1705534 # Number of squashed instructions skipped in execute
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iew.exec_nop 104789 # number of nop insts executed
|
|
|
|
|
system.cpu1.iew.exec_refs 50204478 # number of memory reference insts executed
|
|
|
|
|
system.cpu1.iew.exec_branches 6908033 # Number of branches executed
|
|
|
|
|
system.cpu1.iew.exec_stores 7113462 # Number of stores executed
|
|
|
|
|
system.cpu1.iew.exec_rate 0.211620 # Inst execution rate
|
|
|
|
|
system.cpu1.iew.wb_sent 85323128 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu1.iew.wb_count 53233499 # cumulative count of insts written-back
|
|
|
|
|
system.cpu1.iew.wb_producers 29734399 # num instructions producing a value
|
|
|
|
|
system.cpu1.iew.wb_consumers 53052149 # num instructions consuming a value
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.iew.wb_rate 0.130842 # insts written-back per cycle
|
|
|
|
|
system.cpu1.iew.wb_fanout 0.560475 # average fanout of values written-back
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.commit.commitSquashedInsts 13410332 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu1.commit.commitNonSpecStalls 880845 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu1.commit.branchMispredicts 313641 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::samples 109924338 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::mean 0.438116 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.408415 # Number of insts commited each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.commit.committed_per_cycle::0 93165965 84.75% 84.75% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::1 8233685 7.49% 92.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::2 2134554 1.94% 94.19% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::3 1255111 1.14% 95.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::4 1238932 1.13% 96.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::5 576271 0.52% 96.98% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::6 972518 0.88% 97.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::7 559108 0.51% 98.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::8 1788194 1.63% 100.00% # Number of insts commited each cycle
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.commit.committed_per_cycle::total 109924338 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committedInsts 38068175 # Number of instructions committed
|
|
|
|
|
system.cpu1.commit.committedOps 48159625 # Number of ops (including micro ops) committed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.commit.refs 16597064 # Number of memory references committed
|
|
|
|
|
system.cpu1.commit.loads 9756230 # Number of loads committed
|
|
|
|
|
system.cpu1.commit.membars 190160 # Number of memory barriers committed
|
|
|
|
|
system.cpu1.commit.branches 5968166 # Number of branches committed
|
|
|
|
|
system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu1.commit.int_insts 42694155 # Number of committed integer instructions.
|
|
|
|
|
system.cpu1.commit.function_calls 534687 # Number of function calls committed.
|
|
|
|
|
system.cpu1.commit.bw_lim_events 1788194 # number cycles where commit BW limit reached
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.rob.rob_reads 168661953 # The number of ROB reads
|
|
|
|
|
system.cpu1.rob.rob_writes 125442140 # The number of ROB writes
|
|
|
|
|
system.cpu1.timesIdled 1407356 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu1.idleCycles 294720202 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu1.quiesceCycles 1778443945 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
|
|
|
system.cpu1.committedInsts 37998536 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.committedOps 48089986 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu1.committedInsts_total 37998536 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.cpi 10.707108 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu1.cpi_total 10.707108 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu1.ipc 0.093396 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu1.ipc_total 0.093396 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu1.int_regfile_reads 385381686 # number of integer regfile reads
|
|
|
|
|
system.cpu1.int_regfile_writes 55406618 # number of integer regfile writes
|
|
|
|
|
system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads
|
|
|
|
|
system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes
|
|
|
|
|
system.cpu1.misc_regfile_reads 18496665 # number of misc regfile reads
|
|
|
|
|
system.cpu1.misc_regfile_writes 405533 # number of misc regfile writes
|
|
|
|
|
system.cpu1.icache.replacements 597187 # number of replacements
|
|
|
|
|
system.cpu1.icache.tagsinuse 480.515152 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 6939274 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.sampled_refs 597699 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.avg_refs 11.609981 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 74121232000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 480.515152 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.938506 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_percent::total 0.938506 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 6939274 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::total 6939274 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.demand_hits::cpu1.inst 6939274 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_hits::total 6939274 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.overall_hits::cpu1.inst 6939274 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_hits::total 6939274 # number of overall hits
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 642651 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::total 642651 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.demand_misses::cpu1.inst 642651 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_misses::total 642651 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.overall_misses::cpu1.inst 642651 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_misses::total 642651 # number of overall misses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8610286993 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::total 8610286993 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 8610286993 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::total 8610286993 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 8610286993 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::total 8610286993 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 7581925 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::total 7581925 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 7581925 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_accesses::total 7581925 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 7581925 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::total 7581925 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084761 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.084761 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084761 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::total 0.084761 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084761 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::total 0.084761 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13398.076083 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13398.076083 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13398.076083 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13398.076083 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 2076 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 753 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.069767 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets 753 # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44927 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 44927 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 44927 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits::total 44927 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 44927 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits::total 44927 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 597724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 597724 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::total 597724 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 597724 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::total 597724 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7047898994 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7047898994 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7047898994 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 7047898994 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7047898994 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 7047898994 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078835 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.078835 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.078835 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11791.226375 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dcache.replacements 360661 # number of replacements
|
|
|
|
|
system.cpu1.dcache.tagsinuse 473.725553 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 12688668 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.sampled_refs 361027 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.avg_refs 35.146036 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 70279173000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 473.725553 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.925245 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_percent::total 0.925245 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 8315910 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::total 8315910 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4141838 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::total 4141838 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97575 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 97575 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94901 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::total 94901 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::cpu1.data 12457748 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::total 12457748 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::cpu1.data 12457748 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::total 12457748 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 397655 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::total 397655 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1555408 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::total 1555408 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10609 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10609 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::cpu1.data 1953063 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::total 1953063 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::cpu1.data 1953063 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::total 1953063 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5962620500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 5962620500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 63820949998 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 63820949998 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128371500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 128371500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53750500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 53750500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 69783570498 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::total 69783570498 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 69783570498 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::total 69783570498 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 8713565 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::total 8713565 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697246 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::total 5697246 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111512 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 111512 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105510 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 105510 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 14410811 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.demand_accesses::total 14410811 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 14410811 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::total 14410811 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045636 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.045636 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273011 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.273011 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124982 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124982 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100550 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100550 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135528 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::total 0.135528 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135528 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::total 0.135528 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14994.456250 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14994.456250 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41031.645715 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41031.645715 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9210.841645 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9210.841645 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5066.500141 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5066.500141 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 35730.322318 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 35730.322318 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 26431 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 15171 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_targets 158 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.193118 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 96.018987 # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.dcache.writebacks::writebacks 324726 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.writebacks::total 324726 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169327 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 169327 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393847 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 1393847 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563174 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.dcache.demand_mshr_hits::total 1563174 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563174 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.dcache.overall_mshr_hits::total 1563174 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228328 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 228328 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161561 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 161561 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12488 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12488 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10607 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10607 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 389889 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::total 389889 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 389889 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::total 389889 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2825835000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2825835000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5223945209 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5223945209 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87441500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87441500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32536500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32536500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049780209 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 8049780209 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049780209 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 8049780209 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168995979000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168995979000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27123329043 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27123329043 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196119308043 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196119308043 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026204 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026204 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028358 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028358 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111988 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111988 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100531 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100531 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027055 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.027055 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.208787 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12376.208787 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32334.197046 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32334.197046 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7002.041960 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7002.041960 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3067.455454 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3067.455454 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 497798121418 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 497798121418 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 497798121418 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::total 497798121418 # number of overall MSHR uncacheable cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu0.kern.inst.quiesce 41715 # number of quiesce instructions executed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed
|
2011-08-19 22:08:09 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
