2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2012-03-21 16:36:45 +01:00
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sim_seconds 0.735495 # Number of seconds simulated
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sim_ticks 735495062500 # Number of ticks simulated
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final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-05-09 20:52:14 +02:00
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host_inst_rate 70506 # Simulator instruction rate (inst/s)
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host_op_rate 96019 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 37458496 # Simulator tick rate (ticks/s)
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host_mem_usage 237496 # Number of bytes of host memory used
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host_seconds 19634.93 # Real time elapsed on the host
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2012-03-21 16:36:45 +01:00
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sim_insts 1384379503 # Number of instructions simulated
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sim_ops 1885334256 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 94839680 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_written 4230336 # Number of bytes written to this memory
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2012-03-21 16:36:45 +01:00
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system.physmem.num_reads 1481870 # Number of read requests responded to by this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.num_writes 66099 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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2012-03-21 16:36:45 +01:00
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system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s)
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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2012-03-21 16:36:45 +01:00
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system.cpu.numCycles 1470990126 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-03-21 16:36:45 +01:00
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system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-03-21 16:36:45 +01:00
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system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2012-03-21 16:36:45 +01:00
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system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-03-21 16:36:45 +01:00
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system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2012-03-21 16:36:45 +01:00
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system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2012-03-21 16:36:45 +01:00
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system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-03-21 16:36:45 +01:00
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system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
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|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.847748 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iew.exec_nop 77258 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 359930496 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 479754342 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.779747 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1472840060 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committedInsts 1384390519 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.refs 908386041 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 631388963 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.branches 291350326 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.rob.rob_reads 4369697780 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 6568059146 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1384379503 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 29072 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 414707364 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 414707364 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 414707364 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 36576 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.replacements 1532415 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 1032932504 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 1032932504 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 1032932504 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2368566 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 2368566 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3189668 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3189668 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3189668 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 106560 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1648210 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463799 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1463799 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1541458 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles
|
2012-03-09 21:33:07 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.replacements 1480284 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 61.172380 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28946.522403 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.090509 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001867 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.883378 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.975754 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 27428 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 51328 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 78756 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 106560 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 106560 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6632 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 6632 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 27428 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 57960 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 85388 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 27428 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 57960 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 85388 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3348 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1412471 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 1415819 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4944 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 4944 # number of UpgradeReq misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3348 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 1478551 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 1481899 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3348 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 1478551 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 1481899 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 114766000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48456356500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 48571122500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252292000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2252292000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 114766000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 50708648500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 50823414500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 114766000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 50708648500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 50823414500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30776 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1463799 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1494575 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 106560 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 106560 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4947 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 4947 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72712 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 72712 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 30776 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1536511 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 1567287 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 30776 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1536511 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
|
2012-03-09 21:33:07 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
|
2012-03-09 21:33:07 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
|
2012-03-09 21:33:07 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3343 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412447 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1415790 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4944 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4944 # number of UpgradeReq MSHR misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3343 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1478527 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 1481870 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3343 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1478527 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 1481870 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103877000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43883033500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43986910500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 153264000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 153264000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048525000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
2012-03-21 16:36:45 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
