gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.593146                       # Number of seconds simulated
sim_ticks                                2593146078000                       # Number of ticks simulated
final_tick                               2593146078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  66425                       # Simulator instruction rate (inst/s)
host_op_rate                                    85503                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2731005239                       # Simulator tick rate (ticks/s)
host_mem_usage                                 409388                       # Number of bytes of host memory used
host_seconds                                   949.52                       # Real time elapsed on the host
sim_insts                                    63072130                       # Number of instructions simulated
sim_ops                                      81187111                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           395328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4376500                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           426752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5261232                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131572388                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       395328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       426752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          822080                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4282048                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7311184                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6177                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             68455                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6668                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82233                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15302381                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66907                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               824191                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46704090                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           346                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              152451                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1687718                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           370                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              164569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2028899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50738518                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         152451                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         164569                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             317020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1651295                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6556                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1161576                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2819426                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1651295                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46704090                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          346                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             152451                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1694274                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          370                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             164569                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3190475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53557944                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15302381                       # Total number of read requests seen
system.physmem.writeReqs                       824191                       # Total number of write requests seen
system.physmem.cpureqs                         284713                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    979352384                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52748224                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              131572388                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7311184                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      335                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              14131                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                956528                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                956655                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                956404                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                956499                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                956473                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                956086                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                955879                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                956080                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                957009                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                956354                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               956393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               956606                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               956350                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               956542                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               956247                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               955941                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50875                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 51001                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50801                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 50933                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51869                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51569                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51383                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51546                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 52151                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51788                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51664                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51769                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51735                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51864                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51697                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51546                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                     1150487                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2593144762500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                     105                       # Categorize read packet sizes
system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  163460                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                1907771                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  66907                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                14131                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                  15151641                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     94331                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8809                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3486                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2848                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2557                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2313                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1368                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     6472                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     9621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    13063                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      592                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    31808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    31587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    31428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    31249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                    47868619345                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              322210199345                       # Sum of mem lat for all requests
system.physmem.totBusLat                  61208184000                       # Total cycles spent in databus access
system.physmem.totBankLat                213133396000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3128.25                       # Average queueing delay per request
system.physmem.avgBankLat                    13928.42                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  21056.67                       # Average memory access latency
system.physmem.avgRdBW                         377.67                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.34                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  50.74                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.82                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.49                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.12                       # Average read queue length over time
system.physmem.avgWrQLen                        10.88                       # Average write queue length over time
system.physmem.readRowHits                   15253448                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    789566                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.68                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  95.80                       # Row buffer hit rate for writes
system.physmem.avgGap                       160799.50                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          148                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              173                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          148                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          173                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          148                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             173                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         73184                       # number of replacements
system.l2c.tagsinuse                     53096.266008                       # Cycle average of tags in use
system.l2c.total_refs                         1906265                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        138351                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.778469                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        37733.790025                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       7.219153                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.000341                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4206.047810                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2960.317078                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      11.178862                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.966447                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          4058.933416                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          4117.812877                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.575772                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000110                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.064179                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.045171                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000171                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.061934                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.062833                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.810185                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        33579                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4963                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             393016                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             165084                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        53008                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6038                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             608232                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             201468                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1465388                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          583960                       # number of Writeback hits
system.l2c.Writeback_hits::total               583960                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1107                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             848                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1955                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           209                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           159                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               368                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            47823                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            59123                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106946                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         33579                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4963                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              393016                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              212907                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         53008                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6038                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              608232                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              260591                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1572334                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        33579                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4963                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             393016                       # number of overall hits
system.l2c.overall_hits::cpu0.data             212907                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        53008                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6038                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             608232                       # number of overall hits
system.l2c.overall_hits::cpu1.data             260591                       # number of overall hits
system.l2c.overall_hits::total                1572334                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6056                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6345                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             6633                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             6362                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                25428                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5684                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4404                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             10088                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          773                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          585                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1358                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63519                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          77106                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140625                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6056                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             69864                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6633                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             83468                       # number of demand (read+write) misses
system.l2c.demand_misses::total                166053                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6056                       # number of overall misses
system.l2c.overall_misses::cpu0.data            69864                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6633                       # number of overall misses
system.l2c.overall_misses::cpu1.data            83468                       # number of overall misses
system.l2c.overall_misses::total               166053                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1175500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       118000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    320358500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    344253498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1038500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       122500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    371653000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    369594500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1408313998                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9084989                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12192500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21277489                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       591000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2932000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3523000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3155374488                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4272368491                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7427742979                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1175500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       118000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    320358500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3499627986                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1038500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       122500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    371653000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4641962991                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8836056977                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1175500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       118000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    320358500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3499627986                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1038500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       122500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    371653000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4641962991                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8836056977                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        33593                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         4965                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         399072                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         171429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        53023                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6039                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         614865                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         207830                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1490816                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       583960                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           583960                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6791                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5252                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           12043                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          982                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          744                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1726                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       111342                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       136229                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247571                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        33593                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4965                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          399072                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          282771                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        53023                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6039                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          614865                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          344059                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1738387                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        33593                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4965                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         399072                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         282771                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        53023                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6039                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         614865                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         344059                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1738387                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000417                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000403                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015175                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.037012                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000283                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000166                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010788                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.030612                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017056                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.836990                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.838538                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.837665                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787169                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.786290                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.786790                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.570486                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.566003                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.568019                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000417                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000403                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015175                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.247069                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000283                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000166                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010788                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.242598                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.095521                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000417                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000403                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015175                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.247069                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000283                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000166                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010788                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.242598                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.095521                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83964.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        59000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52899.356011                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 54255.870449                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69233.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       122500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56030.906076                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58094.074191                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 55384.379346                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1598.344300                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2768.505904                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2109.188045                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   764.553687                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5011.965812                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2594.256259                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49676.073112                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55409.027715                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52819.505628                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83964.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52899.356011                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50092.007128                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69233.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       122500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 56030.906076                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 55613.684178                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53212.269438                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83964.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        59000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52899.356011                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50092.007128                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69233.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       122500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 56030.906076                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 55613.684178                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53212.269438                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               66907                       # number of writebacks
system.l2c.writebacks::total                    66907                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            25                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                75                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6053                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6306                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         6625                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         6337                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25353                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5684                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4404                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        10088                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          773                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          585                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1358                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        63519                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        77106                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140625                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6053                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        69825                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6625                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        83443                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           165978                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6053                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        69825                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6625                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        83443                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          165978                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       998025                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    243809691                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    262215347                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       849526                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       109502                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    287575375                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    287912849                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1083563317                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57255976                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44756275                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    102012251                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7762758                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5877575                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     13640333                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2369346199                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3313598990                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5682945189                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       998025                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    243809691                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2631561546                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       849526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       109502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    287575375                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3601511839                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6766508506                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       998025                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    243809691                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2631561546                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       849526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       109502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    287575375                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3601511839                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6766508506                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      4558163                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12330302064                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      1815064                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154912119500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167248794791                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1062521236                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  17116054868                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  18178576104                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      4558163                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13392823300                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      1815064                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172028174368                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 185427370895                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000417                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000403                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015168                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036785                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000283                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000166                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010775                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030491                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017006                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.836990                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.838538                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.837665                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787169                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.786290                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.786790                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.570486                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.566003                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.568019                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000417                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000403                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015168                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.246931                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000283                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000166                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010775                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.242525                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.095478                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000417                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000403                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015168                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.246931                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000283                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000166                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010775                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.242525                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.095478                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       109502                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       109502                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40767.502356                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       109502                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40767.502356                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     9014303                       # DTB read hits
system.cpu0.dtb.read_misses                     34965                       # DTB read misses
system.cpu0.dtb.write_hits                    5253714                       # DTB write hits
system.cpu0.dtb.write_misses                     6399                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2155                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1094                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   321                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      573                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 9049268                       # DTB read accesses
system.cpu0.dtb.write_accesses                5260113                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14268017                       # DTB hits
system.cpu0.dtb.misses                          41364                       # DTB misses
system.cpu0.dtb.accesses                     14309381                       # DTB accesses
system.cpu0.itb.inst_hits                     4294311                       # ITB inst hits
system.cpu0.itb.inst_misses                      5261                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1385                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1364                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 4299572                       # ITB inst accesses
system.cpu0.itb.hits                          4294311                       # DTB hits
system.cpu0.itb.misses                           5261                       # DTB misses
system.cpu0.itb.accesses                      4299572                       # DTB accesses
system.cpu0.numCycles                        69013505                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 6123831                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           4675790                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            298271                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              3798227                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 2989296                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  685728                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              28375                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          11998527                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      32710943                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    6123831                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3675024                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      7667644                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1480146                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     66638                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              21758305                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                5862                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        53793                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        90248                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          221                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  4292744                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               155269                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2401                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          42704543                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.988603                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.369673                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                35044149     82.06%     82.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  606065      1.42%     83.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  793528      1.86%     85.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  689319      1.61%     86.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  781424      1.83%     88.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  567584      1.33%     90.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  711320      1.67%     91.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  364019      0.85%     92.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3147135      7.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            42704543                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.088734                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.473979                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                12497333                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             21726841                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  6896095                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               584636                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                999638                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              951812                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                64726                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              40836330                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               213865                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                999638                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                13071648                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                5812993                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      13759259                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  6855374                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              2205631                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              39711904                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 2173                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                427558                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1242268                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents              68                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           40116309                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            179435830                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       179401258                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            34572                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31681024                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 8435284                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            457771                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        414521                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  5443309                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             7819363                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5820332                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1146243                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1242216                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  37575405                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             946067                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 37951575                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            82274                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6366228                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13456450                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        257591                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     42704543                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.888701                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.500077                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           27159670     63.60%     63.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            6000291     14.05%     77.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3232720      7.57%     85.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2489147      5.83%     91.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2132528      4.99%     96.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             950123      2.22%     98.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             497063      1.16%     99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             188710      0.44%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              54291      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       42704543                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  24659      2.31%      2.31% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   467      0.04%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                838061     78.41%     80.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               205631     19.24%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            52344      0.14%      0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             22793341     60.06%     60.20% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48224      0.13%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 1      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.33% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9480747     24.98%     85.31% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5576214     14.69%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              37951575                       # Type of FU issued
system.cpu0.iq.rate                          0.549915                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1068818                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.028163                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         119791525                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         44895833                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     35071497                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads               8304                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              4710                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         3884                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              38963714                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   4335                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          318123                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1396327                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2506                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13403                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       544501                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2149359                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5385                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                999638                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                4184428                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               103741                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           38639126                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts            85944                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              7819363                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5820332                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            614711                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 41414                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 3290                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13403                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        151339                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       119425                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              270764                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             37563861                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9331167                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           387714                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       117654                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14857557                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4958494                       # Number of branches executed
system.cpu0.iew.exec_stores                   5526390                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.544297                       # Inst execution rate
system.cpu0.iew.wb_sent                      37365472                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     35075381                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 18655901                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35819655                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.508239                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.520829                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6205381                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         688476                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           234604                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     41741265                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.766601                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.727877                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     29720457     71.20%     71.20% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      5963123     14.29%     85.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1948324      4.67%     90.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1002440      2.40%     92.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       789371      1.89%     94.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       520489      1.25%     95.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       393953      0.94%     96.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       216687      0.52%     97.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1186421      2.84%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     41741265                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            24264310                       # Number of instructions committed
system.cpu0.commit.committedOps              31998915                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      11698867                       # Number of memory references committed
system.cpu0.commit.loads                      6423036                       # Number of loads committed
system.cpu0.commit.membars                     234373                       # Number of memory barriers committed
system.cpu0.commit.branches                   4346960                       # Number of branches committed
system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 28266871                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              499893                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1186421                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    77875275                       # The number of ROB reads
system.cpu0.rob.rob_writes                   77410136                       # The number of ROB writes
system.cpu0.timesIdled                         364830                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26308962                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5117234895                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   24183568                       # Number of Instructions Simulated
system.cpu0.committedOps                     31918173                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             24183568                       # Number of Instructions Simulated
system.cpu0.cpi                              2.853735                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.853735                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.350418                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.350418                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               175323075                       # number of integer regfile reads
system.cpu0.int_regfile_writes               34853003                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     3246                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     906                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               46878729                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                527371                       # number of misc regfile writes
system.cpu0.icache.replacements                399233                       # number of replacements
system.cpu0.icache.tagsinuse               511.592262                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3861943                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                399745                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.661016                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6802423000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.592262                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.999204                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999204                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3861943                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3861943                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3861943                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3861943                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3861943                       # number of overall hits
system.cpu0.icache.overall_hits::total        3861943                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       430668                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       430668                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       430668                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        430668                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       430668                       # number of overall misses
system.cpu0.icache.overall_misses::total       430668                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5857521993                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5857521993                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5857521993                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5857521993                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5857521993                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5857521993                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      4292611                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      4292611                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      4292611                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      4292611                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      4292611                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      4292611                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100328                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.100328                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100328                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.100328                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100328                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.100328                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13601.015151                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13601.015151                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2687                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              157                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.114650                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        30901                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        30901                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        30901                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        30901                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        30901                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        30901                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       399767                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       399767                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       399767                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       399767                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       399767                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       399767                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4790784994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4790784994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4790784994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4790784994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4790784994                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4790784994                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7139500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7139500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7139500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7139500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093129                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093129                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093129                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.093129                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093129                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.093129                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                274937                       # number of replacements
system.cpu0.dcache.tagsinuse               481.181813                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9516256                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                275449                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 34.548160                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              36452000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   481.181813                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.939808                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.939808                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5887183                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5887183                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3238358                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3238358                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       173666                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       173666                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171542                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       171542                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9125541                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9125541                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9125541                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9125541                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       390766                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       390766                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1582021                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1582021                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8872                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8872                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7743                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7743                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1972787                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1972787                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1972787                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1972787                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5377265000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5377265000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  60881411847                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  60881411847                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     88222500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     88222500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50475500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     50475500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  66258676847                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  66258676847                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  66258676847                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  66258676847                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6277949                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6277949                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4820379                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4820379                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       182538                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       182538                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179285                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       179285                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11098328                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11098328                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11098328                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11098328                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062244                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.062244                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.328194                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.328194                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048604                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048604                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043188                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043188                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.177755                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.177755                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.177755                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.177755                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9943.924707                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9943.924707                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6518.855741                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6518.855741                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         8283                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3369                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              596                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             82                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.897651                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    41.085366                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       255577                       # number of writebacks
system.cpu0.dcache.writebacks::total           255577                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       202032                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       202032                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1450989                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1450989                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          498                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          498                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1653021                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1653021                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1653021                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1653021                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188734                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       188734                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131032                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       131032                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8374                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8374                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7739                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7739                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       319766                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       319766                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       319766                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       319766                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2333622500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2333622500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4054127491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4054127491                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     66245000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     66245000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34997500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34997500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6387749991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6387749991                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6387749991                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6387749991                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13431600500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13431600500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1199905877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1199905877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14631506377                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14631506377                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030063                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030063                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027183                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027183                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.045875                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.045875                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043166                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043166                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028812                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028812                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028812                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028812                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7910.795319                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7910.795319                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4522.225094                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4522.225094                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    43030291                       # DTB read hits
system.cpu1.dtb.read_misses                     42638                       # DTB read misses
system.cpu1.dtb.write_hits                    6991861                       # DTB write hits
system.cpu1.dtb.write_misses                    11867                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2362                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2846                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   322                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      690                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                43072929                       # DTB read accesses
system.cpu1.dtb.write_accesses                7003728                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         50022152                       # DTB hits
system.cpu1.dtb.misses                          54505                       # DTB misses
system.cpu1.dtb.accesses                     50076657                       # DTB accesses
system.cpu1.itb.inst_hits                     7786412                       # ITB inst hits
system.cpu1.itb.inst_misses                      5635                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1587                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1520                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7792047                       # ITB inst accesses
system.cpu1.itb.hits                          7786412                       # DTB hits
system.cpu1.itb.misses                           5635                       # DTB misses
system.cpu1.itb.accesses                      7792047                       # DTB accesses
system.cpu1.numCycles                       409024249                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 9020667                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           7346445                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            421687                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              5902094                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 5066087                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  810235                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              44717                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          19548819                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      61628162                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    9020667                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           5876322                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13445282                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3432135                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     71958                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              78159434                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5756                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        48212                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       140837                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          164                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  7784486                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               545452                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3066                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         113770833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.663645                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.994153                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               100333102     88.19%     88.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  820750      0.72%     88.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  967014      0.85%     89.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1722421      1.51%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1420935      1.25%     92.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  598048      0.53%     93.05% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1962596      1.73%     94.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  435893      0.38%     95.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5510074      4.84%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           113770833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.022054                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.150671                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                20932611                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             77783544                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12260401                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               543319                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               2250958                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1146967                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               100968                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              71503765                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               336196                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               2250958                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                22152530                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               32126143                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      41276446                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11489660                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4475096                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              67542275                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                19496                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                697256                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3178756                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           32684                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           70870880                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            310023883                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       309964693                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            59190                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             50213421                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                20657459                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            473589                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        413624                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  8131877                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            12919526                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            8160199                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1076421                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1515550                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  62172086                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1201080                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 89161848                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           100982                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       13762748                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     36926540                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        280453                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    113770833                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.783697                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.520241                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           83205809     73.13%     73.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            8622127      7.58%     80.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            4341809      3.82%     84.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3750529      3.30%     87.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           10472490      9.20%     97.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1973623      1.73%     98.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1061651      0.93%     99.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             265825      0.23%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              76970      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      113770833                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  29803      0.38%      0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   992      0.01%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7572506     95.90%     96.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               293239      3.71%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass           314062      0.35%      0.35% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             37491969     42.05%     42.40% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               61148      0.07%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1700      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.47% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            43923048     49.26%     91.73% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            7369892      8.27%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              89161848                       # Type of FU issued
system.cpu1.iq.rate                          0.217987                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    7896540                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.088564                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         300131429                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         77144913                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     54450273                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              14948                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              8092                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         6814                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              96736439                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7887                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          357826                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2919371                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         4089                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        17660                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1133342                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     31965401                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       692354                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               2250958                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               24192691                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               367138                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           63477454                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           113697                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             12919526                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             8160199                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            893697                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 68960                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3858                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         17660                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        208465                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       159370                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              367835                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             87401818                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             43412086                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1760030                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       104288                       # number of nop insts executed
system.cpu1.iew.exec_refs                    50709476                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 7088545                       # Number of branches executed
system.cpu1.iew.exec_stores                   7297390                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.213684                       # Inst execution rate
system.cpu1.iew.wb_sent                      86601126                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     54457087                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 30364436                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 54295656                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.133139                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.559242                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       13692554                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         920627                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           322274                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    111568344                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.442227                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.413238                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     94375668     84.59%     84.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      8446118      7.57%     92.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2197127      1.97%     94.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1290727      1.16%     95.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1277171      1.14%     96.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       591366      0.53%     96.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1009730      0.91%     97.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       541366      0.49%     98.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1839071      1.65%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    111568344                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            38958201                       # Number of instructions committed
system.cpu1.commit.committedOps              49338577                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      17027012                       # Number of memory references committed
system.cpu1.commit.loads                     10000155                       # Number of loads committed
system.cpu1.commit.membars                     202531                       # Number of memory barriers committed
system.cpu1.commit.branches                   6139960                       # Number of branches committed
system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 43727423                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              556605                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1839071                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   171645222                       # The number of ROB reads
system.cpu1.rob.rob_writes                  128401309                       # The number of ROB writes
system.cpu1.timesIdled                        1423775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      295253416                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4776625618                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38888562                       # Number of Instructions Simulated
system.cpu1.committedOps                     49268938                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             38888562                       # Number of Instructions Simulated
system.cpu1.cpi                             10.517855                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                       10.517855                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.095076                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.095076                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               391481129                       # number of integer regfile reads
system.cpu1.int_regfile_writes               56596470                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4905                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2328                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               81326805                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                430176                       # number of misc regfile writes
system.cpu1.icache.replacements                614989                       # number of replacements
system.cpu1.icache.tagsinuse               498.619037                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7122851                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                615501                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 11.572444                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74507010000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   498.619037                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.973865                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.973865                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      7122851                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7122851                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7122851                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7122851                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7122851                       # number of overall hits
system.cpu1.icache.overall_hits::total        7122851                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       661583                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       661583                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       661583                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        661583                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       661583                       # number of overall misses
system.cpu1.icache.overall_misses::total       661583                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8883357995                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8883357995                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8883357995                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8883357995                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8883357995                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8883357995                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7784434                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7784434                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7784434                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7784434                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7784434                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7784434                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.084988                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.084988                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.084988                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.084988                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.084988                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.084988                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13427.427844                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13427.427844                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         3547                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              182                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    19.489011                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46050                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        46050                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        46050                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        46050                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        46050                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        46050                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       615533                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       615533                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       615533                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       615533                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       615533                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       615533                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7269169496                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7269169496                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7269169496                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7269169496                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7269169496                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7269169496                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2823500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2823500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2823500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      2823500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079072                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079072                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079072                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.079072                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079072                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.079072                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                363437                       # number of replacements
system.cpu1.dcache.tagsinuse               485.666262                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                13086846                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                363802                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 35.972441                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           70623957000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   485.666262                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.948567                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.948567                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      8551806                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        8551806                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4291461                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4291461                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       103521                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       103521                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100890                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total       100890                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     12843267                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        12843267                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     12843267                       # number of overall hits
system.cpu1.dcache.overall_hits::total       12843267                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       401802                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       401802                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1565358                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1565358                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14225                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14225                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10942                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10942                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      1967160                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1967160                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      1967160                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1967160                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6026246000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6026246000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  64613580018                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  64613580018                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131651000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    131651000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58881000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     58881000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  70639826018                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  70639826018                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  70639826018                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  70639826018                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      8953608                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      8953608                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      5856819                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      5856819                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       117746                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       117746                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111832                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       111832                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     14810427                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     14810427                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     14810427                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     14810427                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.044876                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.044876                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.267271                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.267271                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120811                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120811                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097843                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097843                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.132823                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.132823                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.132823                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.132823                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9254.903339                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9254.903339                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5381.191738                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5381.191738                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs        28351                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        15005                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3227                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            168                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.785559                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    89.315476                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       328383                       # number of writebacks
system.cpu1.dcache.writebacks::total           328383                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       170419                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       170419                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1402227                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1402227                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1450                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1450                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1572646                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1572646                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1572646                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1572646                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231383                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       231383                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163131                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       163131                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12775                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12775                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10936                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10936                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       394514                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       394514                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       394514                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       394514                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2870368000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2870368000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5301094210                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5301094210                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90117500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90117500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     37009000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     37009000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8171462210                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   8171462210                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8171462210                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   8171462210                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  26947906394                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  26947906394                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025842                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025842                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027853                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027853                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.108496                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.108496                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097790                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097790                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026638                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026638                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026638                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026638                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7054.207436                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7054.207436                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3384.144111                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3384.144111                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1082174693399                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   43757                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   53969                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------