2004-02-04 21:03:50 +01:00
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/*
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2013-10-31 19:41:13 +01:00
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-02-04 21:03:50 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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* Miguel Serrano
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2004-02-04 21:03:50 +01:00
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include <list>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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2010-09-10 23:58:04 +02:00
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#include "base/intmath.hh"
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2004-02-04 21:03:50 +01:00
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#include "base/misc.hh"
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2010-09-10 23:58:04 +02:00
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#include "base/str.hh"
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2004-02-04 21:03:50 +01:00
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#include "base/trace.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/PCIDEV.hh"
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2010-09-10 23:58:04 +02:00
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#include "dev/alpha/tsunamireg.h"
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2004-02-04 21:03:50 +01:00
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#include "dev/pciconfigall.hh"
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2006-04-20 23:14:30 +02:00
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#include "dev/pcidev.hh"
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#include "mem/packet.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet_access.hh"
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2006-04-20 23:14:30 +02:00
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#include "sim/byteswap.hh"
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2007-03-06 20:13:43 +01:00
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#include "sim/core.hh"
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2004-02-04 21:03:50 +01:00
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2013-07-12 04:56:50 +02:00
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PciDevice::PciConfigPort::PciConfigPort(PciDevice *dev, int busid, int devid,
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2006-07-06 20:41:01 +02:00
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int funcid, Platform *p)
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2008-10-09 13:58:24 +02:00
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: SimpleTimingPort(dev->name() + "-pciconf", dev), device(dev),
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platform(p), busId(busid), deviceId(devid), functionId(funcid)
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2006-04-20 23:14:30 +02:00
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{
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2009-02-01 09:02:21 +01:00
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configAddr = platform->calcPciConfigAddr(busId, deviceId, functionId);
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2006-07-06 20:41:01 +02:00
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}
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2005-11-21 06:38:53 +01:00
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2006-07-06 20:41:01 +02:00
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Tick
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2013-07-12 04:56:50 +02:00
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PciDevice::PciConfigPort::recvAtomic(PacketPtr pkt)
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2006-07-06 20:41:01 +02:00
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{
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2006-08-30 18:57:46 +02:00
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assert(pkt->getAddr() >= configAddr &&
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pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
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2013-02-19 11:56:06 +01:00
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// @todo someone should pay for this
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2015-02-11 16:23:47 +01:00
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pkt->headerDelay = pkt->payloadDelay = 0;
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2006-08-31 01:24:26 +02:00
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return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
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2006-04-20 23:14:30 +02:00
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}
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2005-11-21 06:38:53 +01:00
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2012-01-17 19:55:09 +01:00
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AddrRangeList
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2013-07-12 04:56:50 +02:00
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PciDevice::PciConfigPort::getAddrRanges() const
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2006-04-20 23:14:30 +02:00
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{
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2012-01-17 19:55:09 +01:00
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AddrRangeList ranges;
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2010-11-15 21:04:03 +01:00
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if (configAddr != ULL(-1))
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2012-01-17 19:55:09 +01:00
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ranges.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
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return ranges;
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2006-07-06 20:41:01 +02:00
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}
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2005-11-21 06:38:53 +01:00
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2013-07-12 04:56:50 +02:00
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PciDevice::PciDevice(const Params *p)
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2013-10-31 19:41:13 +01:00
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: DmaDevice(p),
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PMCAP_BASE(p->PMCAPBaseOffset),
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2014-10-16 11:49:57 +02:00
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PMCAP_ID_OFFSET(p->PMCAPBaseOffset+PMCAP_ID),
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PMCAP_PC_OFFSET(p->PMCAPBaseOffset+PMCAP_PC),
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PMCAP_PMCS_OFFSET(p->PMCAPBaseOffset+PMCAP_PMCS),
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2013-10-31 19:41:13 +01:00
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MSICAP_BASE(p->MSICAPBaseOffset),
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MSIXCAP_BASE(p->MSIXCAPBaseOffset),
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2014-10-16 11:49:57 +02:00
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MSIXCAP_ID_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_ID),
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MSIXCAP_MXC_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MXC),
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MSIXCAP_MTAB_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MTAB),
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MSIXCAP_MPBA_OFFSET(p->MSIXCAPBaseOffset+MSIXCAP_MPBA),
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2013-10-31 19:41:13 +01:00
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PXCAP_BASE(p->PXCAPBaseOffset),
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platform(p->platform),
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pioDelay(p->pio_latency),
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2012-02-24 17:43:53 +01:00
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configDelay(p->config_latency),
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configPort(this, params()->pci_bus, params()->pci_dev,
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params()->pci_func, params()->platform)
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2006-04-20 23:14:30 +02:00
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{
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2007-08-16 22:49:05 +02:00
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config.vendor = htole(p->VendorID);
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config.device = htole(p->DeviceID);
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config.command = htole(p->Command);
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config.status = htole(p->Status);
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config.revision = htole(p->Revision);
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config.progIF = htole(p->ProgIF);
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config.subClassCode = htole(p->SubClassCode);
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config.classCode = htole(p->ClassCode);
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config.cacheLineSize = htole(p->CacheLineSize);
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config.latencyTimer = htole(p->LatencyTimer);
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config.headerType = htole(p->HeaderType);
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config.bist = htole(p->BIST);
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config.baseAddr[0] = htole(p->BAR0);
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config.baseAddr[1] = htole(p->BAR1);
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config.baseAddr[2] = htole(p->BAR2);
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config.baseAddr[3] = htole(p->BAR3);
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config.baseAddr[4] = htole(p->BAR4);
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config.baseAddr[5] = htole(p->BAR5);
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config.cardbusCIS = htole(p->CardbusCIS);
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config.subsystemVendorID = htole(p->SubsystemVendorID);
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config.subsystemID = htole(p->SubsystemID);
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config.expansionROM = htole(p->ExpansionROM);
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2013-10-31 19:41:13 +01:00
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config.capabilityPtr = htole(p->CapabilityPtr);
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// Zero out the 7 bytes of reserved space in the PCI Config space register.
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bzero(config.reserved, 7*sizeof(uint8_t));
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2007-08-16 22:49:05 +02:00
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config.interruptLine = htole(p->InterruptLine);
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config.interruptPin = htole(p->InterruptPin);
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config.minimumGrant = htole(p->MinimumGrant);
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config.maximumLatency = htole(p->MaximumLatency);
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2013-10-31 19:41:13 +01:00
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// Initialize the capability lists
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// These structs are bitunions, meaning the data is stored in host
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// endianess and must be converted to Little Endian when accessed
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// by the guest
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// PMCAP
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2014-10-16 11:49:57 +02:00
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pmcap.pid = (uint16_t)p->PMCAPCapId; // pid.cid
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pmcap.pid |= (uint16_t)p->PMCAPNextCapability << 8; //pid.next
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2013-10-31 19:41:13 +01:00
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pmcap.pc = p->PMCAPCapabilities;
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pmcap.pmcs = p->PMCAPCtrlStatus;
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// MSICAP
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2014-10-16 11:49:57 +02:00
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msicap.mid = (uint16_t)p->MSICAPCapId; //mid.cid
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msicap.mid |= (uint16_t)p->MSICAPNextCapability << 8; //mid.next
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2013-10-31 19:41:13 +01:00
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msicap.mc = p->MSICAPMsgCtrl;
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msicap.ma = p->MSICAPMsgAddr;
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msicap.mua = p->MSICAPMsgUpperAddr;
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msicap.md = p->MSICAPMsgData;
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msicap.mmask = p->MSICAPMaskBits;
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msicap.mpend = p->MSICAPPendingBits;
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// MSIXCAP
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2014-10-16 11:49:57 +02:00
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msixcap.mxid = (uint16_t)p->MSIXCAPCapId; //mxid.cid
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msixcap.mxid |= (uint16_t)p->MSIXCAPNextCapability << 8; //mxid.next
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2013-10-31 19:41:13 +01:00
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msixcap.mxc = p->MSIXMsgCtrl;
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msixcap.mtab = p->MSIXTableOffset;
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msixcap.mpba = p->MSIXPbaOffset;
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// allocate MSIX structures if MSIXCAP_BASE
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// indicates the MSIXCAP is being used by having a
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// non-zero base address.
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// The MSIX tables are stored by the guest in
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// little endian byte-order as according the
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// PCIe specification. Make sure to take the proper
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// actions when manipulating these tables on the host
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2014-10-16 11:49:57 +02:00
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uint16_t msixcap_mxc_ts = msixcap.mxc & 0x07ff;
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2013-10-31 19:41:13 +01:00
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if (MSIXCAP_BASE != 0x0) {
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2014-10-16 11:49:57 +02:00
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int msix_vecs = msixcap_mxc_ts + 1;
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2013-10-31 19:41:13 +01:00
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MSIXTable tmp1 = {{0UL,0UL,0UL,0UL}};
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msix_table.resize(msix_vecs, tmp1);
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MSIXPbaEntry tmp2 = {0};
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int pba_size = msix_vecs / MSIXVECS_PER_PBA;
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if ((msix_vecs % MSIXVECS_PER_PBA) > 0) {
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pba_size++;
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}
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msix_pba.resize(pba_size, tmp2);
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}
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2014-10-16 11:49:57 +02:00
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MSIX_TABLE_OFFSET = msixcap.mtab & 0xfffffffc;
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MSIX_TABLE_END = MSIX_TABLE_OFFSET +
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(msixcap_mxc_ts + 1) * sizeof(MSIXTable);
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MSIX_PBA_OFFSET = msixcap.mpba & 0xfffffffc;
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MSIX_PBA_END = MSIX_PBA_OFFSET +
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((msixcap_mxc_ts + 1) / MSIXVECS_PER_PBA)
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* sizeof(MSIXPbaEntry);
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if (((msixcap_mxc_ts + 1) % MSIXVECS_PER_PBA) > 0) {
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MSIX_PBA_END += sizeof(MSIXPbaEntry);
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}
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2013-10-31 19:41:13 +01:00
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// PXCAP
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2014-10-16 11:49:57 +02:00
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pxcap.pxid = (uint16_t)p->PXCAPCapId; //pxid.cid
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pxcap.pxid |= (uint16_t)p->PXCAPNextCapability << 8; //pxid.next
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2013-10-31 19:41:13 +01:00
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pxcap.pxcap = p->PXCAPCapabilities;
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pxcap.pxdcap = p->PXCAPDevCapabilities;
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pxcap.pxdc = p->PXCAPDevCtrl;
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pxcap.pxds = p->PXCAPDevStatus;
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pxcap.pxlcap = p->PXCAPLinkCap;
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pxcap.pxlc = p->PXCAPLinkCtrl;
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pxcap.pxls = p->PXCAPLinkStatus;
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pxcap.pxdcap2 = p->PXCAPDevCap2;
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pxcap.pxdc2 = p->PXCAPDevCtrl2;
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2007-08-16 22:49:05 +02:00
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BARSize[0] = p->BAR0Size;
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BARSize[1] = p->BAR1Size;
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BARSize[2] = p->BAR2Size;
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BARSize[3] = p->BAR3Size;
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BARSize[4] = p->BAR4Size;
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BARSize[5] = p->BAR5Size;
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2009-02-01 09:02:21 +01:00
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legacyIO[0] = p->BAR0LegacyIO;
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legacyIO[1] = p->BAR1LegacyIO;
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legacyIO[2] = p->BAR2LegacyIO;
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legacyIO[3] = p->BAR3LegacyIO;
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legacyIO[4] = p->BAR4LegacyIO;
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legacyIO[5] = p->BAR5LegacyIO;
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2007-08-16 22:49:05 +02:00
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for (int i = 0; i < 6; ++i) {
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2009-02-01 09:02:21 +01:00
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if (legacyIO[i]) {
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2014-09-03 13:43:06 +02:00
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BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
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2009-02-01 09:02:21 +01:00
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config.baseAddr[i] = 0;
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} else {
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BARAddrs[i] = 0;
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uint32_t barsize = BARSize[i];
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if (barsize != 0 && !isPowerOf2(barsize)) {
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fatal("BAR %d size %d is not a power of 2\n", i, BARSize[i]);
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}
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2007-08-16 22:49:05 +02:00
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}
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}
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2005-11-21 06:38:53 +01:00
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2011-10-04 11:26:03 +02:00
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platform->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
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2007-08-16 22:49:05 +02:00
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letoh(config.interruptLine));
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2006-04-20 23:14:30 +02:00
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}
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2005-11-21 06:38:53 +01:00
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2004-02-04 21:03:50 +01:00
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void
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2013-07-12 04:56:50 +02:00
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PciDevice::init()
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2004-02-04 21:03:50 +01:00
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{
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2012-02-24 17:43:53 +01:00
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if (!configPort.isConnected())
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2012-01-17 19:55:09 +01:00
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panic("PCI config port on %s not connected to anything!\n", name());
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2012-02-24 17:43:53 +01:00
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configPort.sendRangeChange();
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DmaDevice::init();
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2006-07-06 20:41:01 +02:00
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}
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2006-07-13 02:22:07 +02:00
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unsigned int
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2013-07-12 04:56:50 +02:00
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PciDevice::drain(DrainManager *dm)
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2006-07-13 02:22:07 +02:00
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{
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unsigned int count;
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2012-11-02 17:32:01 +01:00
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count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
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2006-07-13 02:22:07 +02:00
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if (count)
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2012-11-02 17:32:01 +01:00
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setDrainState(Drainable::Draining);
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2006-07-13 02:22:07 +02:00
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else
|
2012-11-02 17:32:01 +01:00
|
|
|
setDrainState(Drainable::Drained);
|
2006-07-13 02:22:07 +02:00
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
Tick
|
2013-07-12 04:56:50 +02:00
|
|
|
PciDevice::readConfig(PacketPtr pkt)
|
2006-07-06 20:41:01 +02:00
|
|
|
{
|
|
|
|
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
|
2014-10-16 11:49:57 +02:00
|
|
|
|
|
|
|
/* Return 0 for accesses to unimplemented PCI configspace areas */
|
|
|
|
if (offset >= PCI_DEVICE_SPECIFIC &&
|
|
|
|
offset < PCI_CONFIG_SIZE) {
|
|
|
|
warn_once("Device specific PCI config space "
|
|
|
|
"not implemented for %s!\n", this->name());
|
|
|
|
switch (pkt->getSize()) {
|
|
|
|
case sizeof(uint8_t):
|
|
|
|
pkt->set<uint8_t>(0);
|
|
|
|
break;
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
pkt->set<uint16_t>(0);
|
|
|
|
break;
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
pkt->set<uint32_t>(0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("invalid access size(?) for PCI configspace!\n");
|
|
|
|
}
|
|
|
|
} else if (offset > PCI_CONFIG_SIZE) {
|
|
|
|
panic("Out-of-range access to PCI config space!\n");
|
|
|
|
}
|
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
switch (pkt->getSize()) {
|
|
|
|
case sizeof(uint8_t):
|
|
|
|
pkt->set<uint8_t>(config.data[offset]);
|
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint8_t>());
|
2004-02-05 08:25:45 +01:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case sizeof(uint16_t):
|
|
|
|
pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
|
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint16_t>());
|
|
|
|
break;
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
|
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint32_t>());
|
2004-02-05 08:25:45 +01:00
|
|
|
break;
|
|
|
|
default:
|
2006-07-06 20:41:01 +02:00
|
|
|
panic("invalid access size(?) for PCI configspace!\n");
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
2007-06-30 19:16:18 +02:00
|
|
|
pkt->makeAtomicResponse();
|
2006-07-06 20:41:01 +02:00
|
|
|
return configDelay;
|
|
|
|
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
|
|
|
|
2012-01-17 19:55:09 +01:00
|
|
|
AddrRangeList
|
2013-07-12 04:56:50 +02:00
|
|
|
PciDevice::getAddrRanges() const
|
2004-02-04 21:03:50 +01:00
|
|
|
{
|
2012-01-17 19:55:09 +01:00
|
|
|
AddrRangeList ranges;
|
2006-07-06 20:41:01 +02:00
|
|
|
int x = 0;
|
|
|
|
for (x = 0; x < 6; x++)
|
|
|
|
if (BARAddrs[x] != 0)
|
2012-01-17 19:55:09 +01:00
|
|
|
ranges.push_back(RangeSize(BARAddrs[x],BARSize[x]));
|
|
|
|
return ranges;
|
2006-04-20 23:14:30 +02:00
|
|
|
}
|
2004-02-04 21:03:50 +01:00
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
Tick
|
2013-07-12 04:56:50 +02:00
|
|
|
PciDevice::writeConfig(PacketPtr pkt)
|
2006-04-20 23:14:30 +02:00
|
|
|
{
|
2006-07-06 20:41:01 +02:00
|
|
|
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
|
2014-10-16 11:49:57 +02:00
|
|
|
|
|
|
|
/* No effect if we write to config space that is not implemented*/
|
|
|
|
if (offset >= PCI_DEVICE_SPECIFIC &&
|
|
|
|
offset < PCI_CONFIG_SIZE) {
|
|
|
|
warn_once("Device specific PCI config space "
|
|
|
|
"not implemented for %s!\n", this->name());
|
|
|
|
switch (pkt->getSize()) {
|
|
|
|
case sizeof(uint8_t):
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("invalid access size(?) for PCI configspace!\n");
|
|
|
|
}
|
|
|
|
} else if (offset > PCI_CONFIG_SIZE) {
|
|
|
|
panic("Out-of-range access to PCI config space!\n");
|
|
|
|
}
|
2005-08-15 22:59:58 +02:00
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
switch (pkt->getSize()) {
|
|
|
|
case sizeof(uint8_t):
|
|
|
|
switch (offset) {
|
|
|
|
case PCI0_INTERRUPT_LINE:
|
|
|
|
config.interruptLine = pkt->get<uint8_t>();
|
2008-12-15 09:47:01 +01:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case PCI_CACHE_LINE_SIZE:
|
|
|
|
config.cacheLineSize = pkt->get<uint8_t>();
|
2008-12-15 09:47:01 +01:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case PCI_LATENCY_TIMER:
|
|
|
|
config.latencyTimer = pkt->get<uint8_t>();
|
|
|
|
break;
|
|
|
|
/* Do nothing for these read-only registers */
|
|
|
|
case PCI0_INTERRUPT_PIN:
|
|
|
|
case PCI0_MINIMUM_GRANT:
|
|
|
|
case PCI0_MAXIMUM_LATENCY:
|
|
|
|
case PCI_CLASS_CODE:
|
|
|
|
case PCI_REVISION_ID:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("writing to a read only register");
|
2006-04-20 23:14:30 +02:00
|
|
|
}
|
2006-07-06 20:41:01 +02:00
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint8_t>());
|
|
|
|
break;
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
switch (offset) {
|
|
|
|
case PCI_COMMAND:
|
|
|
|
config.command = pkt->get<uint8_t>();
|
2008-12-15 09:47:01 +01:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case PCI_STATUS:
|
|
|
|
config.status = pkt->get<uint8_t>();
|
2008-12-15 09:47:01 +01:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case PCI_CACHE_LINE_SIZE:
|
|
|
|
config.cacheLineSize = pkt->get<uint8_t>();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("writing to a read only register");
|
|
|
|
}
|
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint16_t>());
|
|
|
|
break;
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
switch (offset) {
|
|
|
|
case PCI0_BASE_ADDR0:
|
|
|
|
case PCI0_BASE_ADDR1:
|
|
|
|
case PCI0_BASE_ADDR2:
|
|
|
|
case PCI0_BASE_ADDR3:
|
|
|
|
case PCI0_BASE_ADDR4:
|
|
|
|
case PCI0_BASE_ADDR5:
|
2006-08-28 20:17:49 +02:00
|
|
|
{
|
|
|
|
int barnum = BAR_NUMBER(offset);
|
|
|
|
|
2009-02-01 09:02:21 +01:00
|
|
|
if (!legacyIO[barnum]) {
|
|
|
|
// convert BAR values to host endianness
|
|
|
|
uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
|
|
|
|
uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
|
2006-08-28 20:17:49 +02:00
|
|
|
|
2009-02-01 09:02:21 +01:00
|
|
|
uint32_t bar_mask =
|
|
|
|
BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
|
2006-08-28 20:17:49 +02:00
|
|
|
|
2009-02-01 09:02:21 +01:00
|
|
|
// Writing 0xffffffff to a BAR tells the card to set the
|
|
|
|
// value of the bar to a bitmask indicating the size of
|
|
|
|
// memory it needs
|
|
|
|
if (he_new_bar == 0xffffffff) {
|
|
|
|
he_new_bar = ~(BARSize[barnum] - 1);
|
|
|
|
} else {
|
|
|
|
// does it mean something special to write 0 to a BAR?
|
|
|
|
he_new_bar &= ~bar_mask;
|
|
|
|
if (he_new_bar) {
|
|
|
|
BARAddrs[barnum] = BAR_IO_SPACE(he_old_bar) ?
|
|
|
|
platform->calcPciIOAddr(he_new_bar) :
|
|
|
|
platform->calcPciMemAddr(he_new_bar);
|
2012-02-24 17:43:53 +01:00
|
|
|
pioPort.sendRangeChange();
|
2009-02-01 09:02:21 +01:00
|
|
|
}
|
2006-08-28 20:17:49 +02:00
|
|
|
}
|
2009-02-01 09:02:21 +01:00
|
|
|
config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
|
|
|
|
(he_old_bar & bar_mask));
|
2006-07-06 20:41:01 +02:00
|
|
|
}
|
2004-02-05 08:25:45 +01:00
|
|
|
}
|
2006-07-06 20:41:01 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI0_ROM_BASE_ADDR:
|
|
|
|
if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
|
|
|
|
config.expansionROM = htole((uint32_t)0xffffffff);
|
|
|
|
else
|
|
|
|
config.expansionROM = pkt->get<uint32_t>();
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_COMMAND:
|
|
|
|
// This could also clear some of the error bits in the Status
|
|
|
|
// register. However they should never get set, so lets ignore
|
|
|
|
// it for now
|
|
|
|
config.command = pkt->get<uint32_t>();
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DPRINTF(PCIDEV, "Writing to a read only register");
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
2006-07-06 20:41:01 +02:00
|
|
|
DPRINTF(PCIDEV,
|
2006-08-28 19:28:31 +02:00
|
|
|
"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
|
2007-07-24 06:51:38 +02:00
|
|
|
params()->pci_dev, params()->pci_func, offset,
|
2006-07-06 20:41:01 +02:00
|
|
|
(uint32_t)pkt->get<uint32_t>());
|
2004-02-04 21:03:50 +01:00
|
|
|
break;
|
2005-08-15 22:59:58 +02:00
|
|
|
default:
|
2006-07-06 20:41:01 +02:00
|
|
|
panic("invalid access size(?) for PCI configspace!\n");
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
2007-06-30 19:16:18 +02:00
|
|
|
pkt->makeAtomicResponse();
|
2006-07-06 20:41:01 +02:00
|
|
|
return configDelay;
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2013-07-12 04:56:50 +02:00
|
|
|
PciDevice::serialize(std::ostream &os)
|
2004-02-04 21:03:50 +01:00
|
|
|
{
|
2005-08-23 17:45:52 +02:00
|
|
|
SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
|
|
|
|
SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
|
|
|
|
SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
|
2013-10-31 19:41:13 +01:00
|
|
|
|
|
|
|
// serialize the capability list registers
|
|
|
|
paramOut(os, csprintf("pmcap.pid"), uint16_t(pmcap.pid));
|
|
|
|
paramOut(os, csprintf("pmcap.pc"), uint16_t(pmcap.pc));
|
|
|
|
paramOut(os, csprintf("pmcap.pmcs"), uint16_t(pmcap.pmcs));
|
|
|
|
|
|
|
|
paramOut(os, csprintf("msicap.mid"), uint16_t(msicap.mid));
|
|
|
|
paramOut(os, csprintf("msicap.mc"), uint16_t(msicap.mc));
|
|
|
|
paramOut(os, csprintf("msicap.ma"), uint32_t(msicap.ma));
|
|
|
|
SERIALIZE_SCALAR(msicap.mua);
|
|
|
|
paramOut(os, csprintf("msicap.md"), uint16_t(msicap.md));
|
|
|
|
SERIALIZE_SCALAR(msicap.mmask);
|
|
|
|
SERIALIZE_SCALAR(msicap.mpend);
|
|
|
|
|
|
|
|
paramOut(os, csprintf("msixcap.mxid"), uint16_t(msixcap.mxid));
|
|
|
|
paramOut(os, csprintf("msixcap.mxc"), uint16_t(msixcap.mxc));
|
|
|
|
paramOut(os, csprintf("msixcap.mtab"), uint32_t(msixcap.mtab));
|
|
|
|
paramOut(os, csprintf("msixcap.mpba"), uint32_t(msixcap.mpba));
|
|
|
|
|
|
|
|
// Only serialize if we have a non-zero base address
|
|
|
|
if (MSIXCAP_BASE != 0x0) {
|
2014-10-16 11:49:57 +02:00
|
|
|
uint16_t msixcap_mxc_ts = msixcap.mxc & 0x07ff;
|
|
|
|
int msix_array_size = msixcap_mxc_ts + 1;
|
2013-10-31 19:41:13 +01:00
|
|
|
int pba_array_size = msix_array_size/MSIXVECS_PER_PBA;
|
|
|
|
if ((msix_array_size % MSIXVECS_PER_PBA) > 0) {
|
|
|
|
pba_array_size++;
|
|
|
|
}
|
|
|
|
|
|
|
|
SERIALIZE_SCALAR(msix_array_size);
|
|
|
|
SERIALIZE_SCALAR(pba_array_size);
|
|
|
|
|
|
|
|
for (int i = 0; i < msix_array_size; i++) {
|
|
|
|
paramOut(os, csprintf("msix_table[%d].addr_lo", i),
|
|
|
|
msix_table[i].fields.addr_lo);
|
|
|
|
paramOut(os, csprintf("msix_table[%d].addr_hi", i),
|
|
|
|
msix_table[i].fields.addr_hi);
|
|
|
|
paramOut(os, csprintf("msix_table[%d].msg_data", i),
|
|
|
|
msix_table[i].fields.msg_data);
|
|
|
|
paramOut(os, csprintf("msix_table[%d].vec_ctrl", i),
|
|
|
|
msix_table[i].fields.vec_ctrl);
|
|
|
|
}
|
|
|
|
for (int i = 0; i < pba_array_size; i++) {
|
|
|
|
paramOut(os, csprintf("msix_pba[%d].bits", i),
|
|
|
|
msix_pba[i].bits);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
paramOut(os, csprintf("pxcap.pxid"), uint16_t(pxcap.pxid));
|
|
|
|
paramOut(os, csprintf("pxcap.pxcap"), uint16_t(pxcap.pxcap));
|
|
|
|
paramOut(os, csprintf("pxcap.pxdcap"), uint32_t(pxcap.pxdcap));
|
|
|
|
paramOut(os, csprintf("pxcap.pxdc"), uint16_t(pxcap.pxdc));
|
|
|
|
paramOut(os, csprintf("pxcap.pxds"), uint16_t(pxcap.pxds));
|
|
|
|
paramOut(os, csprintf("pxcap.pxlcap"), uint32_t(pxcap.pxlcap));
|
|
|
|
paramOut(os, csprintf("pxcap.pxlc"), uint16_t(pxcap.pxlc));
|
|
|
|
paramOut(os, csprintf("pxcap.pxls"), uint16_t(pxcap.pxls));
|
|
|
|
paramOut(os, csprintf("pxcap.pxdcap2"), uint32_t(pxcap.pxdcap2));
|
|
|
|
paramOut(os, csprintf("pxcap.pxdc2"), uint32_t(pxcap.pxdc2));
|
2004-02-04 21:03:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2013-07-12 04:56:50 +02:00
|
|
|
PciDevice::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-02-04 21:03:50 +01:00
|
|
|
{
|
2005-08-23 17:45:52 +02:00
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UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
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UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
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UNSERIALIZE_ARRAY(config.data,
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sizeof(config.data) / sizeof(config.data[0]));
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2006-10-09 05:18:19 +02:00
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2013-10-31 19:41:13 +01:00
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// unserialize the capability list registers
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uint16_t tmp16;
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uint32_t tmp32;
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paramIn(cp, section, csprintf("pmcap.pid"), tmp16);
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pmcap.pid = tmp16;
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paramIn(cp, section, csprintf("pmcap.pc"), tmp16);
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pmcap.pc = tmp16;
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paramIn(cp, section, csprintf("pmcap.pmcs"), tmp16);
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pmcap.pmcs = tmp16;
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paramIn(cp, section, csprintf("msicap.mid"), tmp16);
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msicap.mid = tmp16;
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paramIn(cp, section, csprintf("msicap.mc"), tmp16);
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msicap.mc = tmp16;
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paramIn(cp, section, csprintf("msicap.ma"), tmp32);
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msicap.ma = tmp32;
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UNSERIALIZE_SCALAR(msicap.mua);
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paramIn(cp, section, csprintf("msicap.md"), tmp16);;
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msicap.md = tmp16;
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UNSERIALIZE_SCALAR(msicap.mmask);
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UNSERIALIZE_SCALAR(msicap.mpend);
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paramIn(cp, section, csprintf("msixcap.mxid"), tmp16);
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msixcap.mxid = tmp16;
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paramIn(cp, section, csprintf("msixcap.mxc"), tmp16);
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msixcap.mxc = tmp16;
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paramIn(cp, section, csprintf("msixcap.mtab"), tmp32);
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msixcap.mtab = tmp32;
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paramIn(cp, section, csprintf("msixcap.mpba"), tmp32);
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msixcap.mpba = tmp32;
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// Only allocate if MSIXCAP_BASE is not 0x0
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if (MSIXCAP_BASE != 0x0) {
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int msix_array_size;
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int pba_array_size;
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UNSERIALIZE_SCALAR(msix_array_size);
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UNSERIALIZE_SCALAR(pba_array_size);
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MSIXTable tmp1 = {{0UL, 0UL, 0UL, 0UL}};
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msix_table.resize(msix_array_size, tmp1);
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MSIXPbaEntry tmp2 = {0};
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msix_pba.resize(pba_array_size, tmp2);
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for (int i = 0; i < msix_array_size; i++) {
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paramIn(cp, section, csprintf("msix_table[%d].addr_lo", i),
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msix_table[i].fields.addr_lo);
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paramIn(cp, section, csprintf("msix_table[%d].addr_hi", i),
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msix_table[i].fields.addr_hi);
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paramIn(cp, section, csprintf("msix_table[%d].msg_data", i),
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msix_table[i].fields.msg_data);
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paramIn(cp, section, csprintf("msix_table[%d].vec_ctrl", i),
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msix_table[i].fields.vec_ctrl);
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}
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for (int i = 0; i < pba_array_size; i++) {
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paramIn(cp, section, csprintf("msix_pba[%d].bits", i),
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msix_pba[i].bits);
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}
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}
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paramIn(cp, section, csprintf("pxcap.pxid"), tmp16);
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pxcap.pxid = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxcap"), tmp16);
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pxcap.pxcap = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxdcap"), tmp32);
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pxcap.pxdcap = tmp32;
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paramIn(cp, section, csprintf("pxcap.pxdc"), tmp16);
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pxcap.pxdc = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxds"), tmp16);
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pxcap.pxds = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxlcap"), tmp32);
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pxcap.pxlcap = tmp32;
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paramIn(cp, section, csprintf("pxcap.pxlc"), tmp16);
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pxcap.pxlc = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxls"), tmp16);
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pxcap.pxls = tmp16;
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paramIn(cp, section, csprintf("pxcap.pxdcap2"), tmp32);
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pxcap.pxdcap2 = tmp32;
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paramIn(cp, section, csprintf("pxcap.pxdc2"), tmp32);
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pxcap.pxdc2 = tmp32;
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pioPort.sendRangeChange();
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2004-02-04 21:03:50 +01:00
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}
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