2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.105045 # Number of seconds simulated
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sim_ticks 105045070000 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 49247 # Simulator instruction rate (inst/s)
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host_tick_rate 23369426 # Simulator tick rate (ticks/s)
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host_mem_usage 262348 # Number of bytes of host memory used
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host_seconds 4494.98 # Real time elapsed on the host
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2011-02-05 09:16:09 +01:00
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sim_insts 221363017 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 400 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 210090141 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued
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system.cpu.iq.rate 1.342042 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads
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|
|
system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 15748098 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 23391917 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.327442 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 222890509 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.count 221363017 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 77165306 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 56649590 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 12326943 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 585604683 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 827851683 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 516476198 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 284804952 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.replacements 4263 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 28884352 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 7220 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.replacements 50 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 70508699 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 7819 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses)
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.writebacks 10 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
|
2011-02-14 02:44:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2876 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5318 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
