2009-05-11 19:38:46 +02:00
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---------- Begin Simulation Statistics ----------
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2010-01-30 05:29:40 +01:00
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sim_seconds 0.000293 # Number of seconds simulated
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sim_ticks 292960 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-09-09 10:35:05 +02:00
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sim_freq 1000000000 # Frequency of simulated ticks
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2012-01-25 18:19:50 +01:00
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host_inst_rate 55801 # Simulator instruction rate (inst/s)
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host_tick_rate 2804966 # Simulator tick rate (ticks/s)
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host_mem_usage 220172 # Number of bytes of host memory used
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host_seconds 0.10 # Real time elapsed on the host
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2011-09-09 10:35:05 +02:00
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sim_insts 5827 # Number of instructions simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 27687 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3658 # Number of bytes written to this memory
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system.physmem.num_reads 6992 # Number of read requests responded to by this memory
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system.physmem.num_writes 925 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s)
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2009-05-11 19:38:46 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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2011-09-09 10:35:05 +02:00
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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2009-05-11 19:38:46 +02:00
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-09-09 10:35:05 +02:00
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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2009-05-11 19:38:46 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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2011-09-09 10:35:05 +02:00
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system.cpu.itb.read_accesses 0 # DTB read accesses
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2009-05-11 19:38:46 +02:00
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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2011-09-09 10:35:05 +02:00
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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2010-01-30 05:29:40 +01:00
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system.cpu.numCycles 292960 # number of cpu cycles simulated
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2011-02-08 04:23:13 +01:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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2011-09-09 10:35:05 +02:00
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2010-01-02 13:06:26 +01:00
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system.cpu.num_insts 5827 # Number of instructions executed
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
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2011-09-09 10:35:05 +02:00
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system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
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system.cpu.num_func_calls 194 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_insts 5126 # number of integer instructions
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2011-09-09 10:35:05 +02:00
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system.cpu.num_fp_insts 2 # number of float instructions
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2011-09-17 18:34:03 +02:00
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system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
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2011-09-09 10:35:05 +02:00
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system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
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2011-02-08 04:23:13 +01:00
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system.cpu.num_mem_refs 2090 # number of memory refs
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2011-09-09 10:35:05 +02:00
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system.cpu.num_load_insts 1164 # Number of load instructions
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2011-02-08 04:23:13 +01:00
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system.cpu.num_store_insts 926 # Number of store instructions
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2011-09-09 10:35:05 +02:00
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 292960 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2009-05-11 19:38:46 +02:00
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---------- End Simulation Statistics ----------
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