gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Jun  4 2012 12:01:47
gem5 started Jun  4 2012 14:45:13
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB:		Passed
SWAP:		Passed
CAS FAIL:	Passed
CAS WORK:	Passed
CASX FAIL:	Passed
CASX WORK:	Passed
LDTX:		Passed
LDTW:		Passed
STTW:		Passed
Done
Exiting @ tick 41800000 because target called exit()
stats: Update stats for final tick and memory bandwidth patches 2012-01-25 18:19:50 +01:00			`gem5 Simulator System. http://gem5.org`
			`gem5 is copyrighted software; use the --copyright option for details.`
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. 2008-07-22 23:00:18 +02:00
all: Update stats for memory per master and total fix. 2012-06-05 07:23:16 +02:00			`gem5 compiled Jun 4 2012 12:01:47`
			`gem5 started Jun 4 2012 14:45:13`
			`gem5 executing on zizzer`
stats: update stats for no_value -> nan Lots of accumulated older changes too. 2012-05-09 20:52:14 +02:00			`command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing`
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. 2008-07-22 23:00:18 +02:00			`Global frequency set at 1000000000000 ticks per second`
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. 2008-11-06 17:11:42 +01:00			`info: Entering event queue @ 0. Starting simulation...`
Added SPARC simple timing regression for insttest --HG-- extra : convert_revision : cb490fd6f1be73b57dceb93edf83d7edc4a67beb 2007-04-09 09:52:15 +02:00			`Begining test of difficult SPARC instructions...`
			`LDSTUB: Passed`
			`SWAP: Passed`
			`CAS FAIL: Passed`
			`CAS WORK: Passed`
			`CASX FAIL: Passed`
			`CASX WORK: Passed`
			`LDTX: Passed`
			`LDTW: Passed`
			`STTW: Passed`
			`Done`
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. 2010-09-09 20:40:19 +02:00			`Exiting @ tick 41800000 because target called exit()`