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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr

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tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
stats: update references
2016-07-21 18:19:18 +02:00
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
stats: overdue updates to long regressions
2016-03-16 21:03:49 +01:00
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0]
warn: instruction 'mcr dcisw' unimplemented
stats: update references
2016-07-21 18:19:18 +02:00
warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
stats: update references
2016-07-21 18:19:18 +02:00
warn: instruction 'mcr bpiall' unimplemented
stats: Update to match ARM ISA changes
2016-06-02 15:14:36 +02:00
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
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