gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr

warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: 	instruction 'mcr dccmvau' unimplemented
warn: 	instruction 'mcr icimvau' unimplemented
warn: 	instruction 'mcr bpiallis' unimplemented
warn: 	instruction 'mcr icialluis' unimplemented
warn: 	instruction 'mcr dccimvac' unimplemented
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
warn: CP14 unimplemented crn[4], opc1[0], crm[12], opc2[1]
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
warn: CP14 unimplemented crn[3], opc1[5], crm[12], opc2[1]
warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
warn: 	instruction 'mcr bpiall' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)`
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover. 2013-01-07 19:05:52 +01:00			`warn: Sockets disabled, not accepting vnc client connections`
			`warn: Sockets disabled, not accepting terminal connections`
			`warn: Sockets disabled, not accepting gdb connections`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: Existing EnergyCtrl, but no enabled DVFSHandler found.`
			`warn: Not doing anything for miscreg ACTLR`
stats: update for previous changeset Very small differences in IQ-specific O3 stats. 2015-04-23 05:22:29 +02:00			`warn: Not doing anything for miscreg ACTLR`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: Not doing anything for write of miscreg ACTLR`
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover. 2013-01-07 19:05:52 +01:00			`warn: The clidr register always reports 0 caches.`
			`warn: clidr LoUIS field of 0b001 to match current ARM implementations.`
			`warn: The csselr register isn't implemented.`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]`
			`warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]`
			`warn: instruction 'mcr dccmvau' unimplemented`
			`warn: instruction 'mcr icimvau' unimplemented`
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover. 2013-01-07 19:05:52 +01:00			`warn: instruction 'mcr bpiallis' unimplemented`
			`warn: instruction 'mcr icialluis' unimplemented`
			`warn: instruction 'mcr dccimvac' unimplemented`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: Tried to read RealView I/O at offset 0x60 that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist`
			`warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]`
			`warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]`
			`warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]`
			`warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]`
			`warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]`
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences. 2014-11-03 17:14:42 +01:00			`warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]`
stats: updates due to recent changesets including d0934b57735a 2015-09-15 15:14:09 +02:00			`warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]`
			`warn: CP14 unimplemented crn[4], opc1[0], crm[12], opc2[1]`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: Returning zero for read from miscreg pmcr`
			`warn: Ignoring write to miscreg pmcntenclr`
			`warn: Ignoring write to miscreg pmintenclr`
			`warn: Ignoring write to miscreg pmovsr`
			`warn: Ignoring write to miscreg pmcr`
			`warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]`
stats: updates due to recent changesets including d0934b57735a 2015-09-15 15:14:09 +02:00			`warn: CP14 unimplemented crn[3], opc1[5], crm[12], opc2[1]`
stats: update stale config.ini files, eio and few other stats. 2015-07-04 17:43:47 +02:00			`warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]`
			`warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]`
stats: updates due to recent changesets including d0934b57735a 2015-09-15 15:14:09 +02:00			`warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]`
tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-30 05:18:29 +01:00			`warn: instruction 'mcr bpiall' unimplemented`
stats: update stats for ARMv8 changes 2014-01-24 22:29:34 +01:00			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
stats: update stale config.ini files, eio and few other stats. 2015-07-04 17:43:47 +02:00			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`
			`warn: User mode does not have SPSR`