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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

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X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
sim_seconds 5.172910 # Number of seconds simulated
sim_ticks 5172910256500 # Number of ticks simulated
final_tick 5172910256500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
host_inst_rate 136129 # Simulator instruction rate (inst/s)
host_op_rate 268264 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1651021148 # Simulator tick rate (ticks/s)
host_mem_usage 373420 # Number of bytes of host memory used
host_seconds 3133.16 # Real time elapsed on the host
sim_insts 426513995 # Number of instructions simulated
sim_ops 840512563 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1067584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10442240 # Number of bytes read from this memory
system.physmem.bytes_read::total 13977280 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1067584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1067584 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9176384 # Number of bytes written to this memory
system.physmem.bytes_written::total 9176384 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38501 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16681 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 163160 # Number of read requests responded to by this memory
system.physmem.num_reads::total 218395 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143381 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 476340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 569 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 206380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2018639 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2702015 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 206380 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 206380 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1773931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1773931 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1773931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 476340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 569 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 206380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2018639 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4475945 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 106892 # number of replacements
system.l2c.tagsinuse 64846.239814 # Cycle average of tags in use
system.l2c.total_refs 3994467 # Total number of references to valid blocks.
system.l2c.sampled_refs 171328 # Sample count of references to valid blocks.
system.l2c.avg_refs 23.314735 # Average number of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.occ_blocks::writebacks 50145.406461 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 11.508776 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.169764 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 3382.865025 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 11306.289787 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.765158 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000176 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.051618 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.172520 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.989475 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 113294 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 9300 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 1056563 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1345318 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2524475 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1607595 # number of Writeback hits
system.l2c.Writeback_hits::total 1607595 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 334 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 334 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 163366 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 163366 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 113294 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 9300 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 1056563 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1508684 # number of demand (read+write) hits
system.l2c.demand_hits::total 2687841 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 113294 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 9300 # number of overall hits
system.l2c.overall_hits::cpu.inst 1056563 # number of overall hits
system.l2c.overall_hits::cpu.data 1508684 # number of overall hits
system.l2c.overall_hits::total 2687841 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 16683 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 35188 # number of ReadReq misses
system.l2c.ReadReq_misses::total 51924 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2935 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2935 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 128896 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 128896 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 16683 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 164084 # number of demand (read+write) misses
system.l2c.demand_misses::total 180820 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses
system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
system.l2c.overall_misses::cpu.inst 16683 # number of overall misses
system.l2c.overall_misses::cpu.data 164084 # number of overall misses
system.l2c.overall_misses::total 180820 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2412500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst 885747500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 1875717995 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2764241995 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 38348000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 38348000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6718316497 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6718316497 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker 2412500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst 885747500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 8594034492 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9482558492 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker 2412500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst 885747500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 8594034492 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9482558492 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker 113340 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 9307 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 1073246 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1380506 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2576399 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1607595 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1607595 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 3269 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3269 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 292262 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 292262 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 113340 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 9307 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 1073246 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1672768 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2868661 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 113340 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 9307 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 1073246 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1672768 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2868661 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000406 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000752 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.015544 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.025489 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020154 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.897828 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.897828 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.441029 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.441029 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000406 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000752 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.015544 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.098091 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.063033 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000406 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000752 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.015544 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.098091 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.063033 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52445.652174 # average ReadReq miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53092.819037 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 53305.615409 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53236.306814 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13065.758092 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13065.758092 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52121.993677 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52121.993677 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52441.978166 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52441.978166 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.writebacks::writebacks 96714 # number of writebacks
system.l2c.writebacks::total 96714 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst 16681 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 35187 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 51921 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 2935 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2935 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 128896 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 128896 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 16681 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 164083 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 180817 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 16681 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 164083 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 180817 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1851000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682272500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1445683499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2130086999 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117833500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 117833500 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5165552500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5165552500 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1851000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 682272500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 6611235999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 7295639499 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1851000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 682272500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 6611235999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 7295639499 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192780564 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 59192780564 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1212414000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1212414000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 60405194564 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60405194564 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025488 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020153 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.897828 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.897828 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.441029 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.441029 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.replacements 47569 # number of replacements
system.iocache.tagsinuse 0.199376 # Cycle average of tags in use
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.warmup_cycle 5000598404000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.199376 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.012461 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.012461 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
system.iocache.overall_misses::total 47624 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135906932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 135906932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6908833160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 6908833160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 7044740092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7044740092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 7044740092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7044740092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 150339.526549 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 147877.422089 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 147924.157820 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 147924.157820 # average overall miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
X86 Regression: update stats due to cc register split
2012-05-22 18:38:04 +02:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88867000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 88867000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4479079912 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4479079912 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4567946912 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4567946912 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.numCycles 473223088 # number of cpu cycles simulated
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.BPredUnit.lookups 90016360 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 90016360 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1178248 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 84343978 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 81707122 # Number of BTB hits
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.fetch.icacheStallCycles 31356562 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 446929489 # Number of instructions fetch has processed
system.cpu.fetch.Branches 90016360 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 81707122 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 169790434 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5330018 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 171751 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 104797996 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 37968 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 45006 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 453 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9363044 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 536807 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5287 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 310312997 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.834177 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.376352 # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.fetch.rateDist::0 140957479 45.42% 45.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1776597 0.57% 46.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 72781994 23.45% 69.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 982988 0.32% 69.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1642902 0.53% 70.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3674853 1.18% 71.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1139478 0.37% 71.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1444103 0.47% 72.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 85912603 27.69% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.fetch.rateDist::total 310312997 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.190220 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.944437 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 36508708 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 100881020 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 164105770 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4704672 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4112827 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 876214899 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4112827 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 40925858 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 44314017 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 11153757 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 163784094 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46022444 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 872421528 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10519 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 35242822 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3962452 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 32001317 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1394162179 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2488413918 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2488413062 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 856 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1347546247 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 46615925 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 471039 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 478955 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48145791 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 18923985 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10455746 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1291287 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1021115 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 865765672 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1722965 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 864313181 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 123185 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26037339 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 53671952 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 207307 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 310312997 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.785295 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.396376 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.issued_per_cycle::0 102585339 33.06% 33.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 23772488 7.66% 40.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 19036495 6.13% 46.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7825788 2.52% 49.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 80603332 25.97% 75.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3104423 1.00% 76.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72752969 23.45% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 520222 0.17% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 111941 0.04% 100.00% # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.issued_per_cycle::total 310312997 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.fu_full::IntAlu 164594 7.88% 7.88% # attempts to use FU when none available
Regression: Update stats due to changes to x86 cpuid instruction
2012-07-23 03:31:24 +02:00
system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.fu_full::MemRead 1764434 84.50% 92.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 159044 7.62% 100.00% # attempts to use FU when none available
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.FU_type_0::No_OpClass 296261 0.03% 0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 829427794 95.96% 96.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.FU_type_0::MemRead 25158656 2.91% 98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9430470 1.09% 100.00% # Type of FU issued
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.FU_type_0::total 864313181 # Type of FU issued
system.cpu.iq.rate 1.826439 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2088072 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002416 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2041288204 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 893536846 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 853917717 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 410 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 866104816 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1579729 # Number of loads that had data forwarded from stores
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 3631905 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20141 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12168 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2053612 # Number of stores squashed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 7821470 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4399 # Number of times an access to memory failed due to the cache being blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iew.iewSquashCycles 4112827 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 27932530 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1927286 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 867488637 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 301587 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 18923985 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10455746 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 885039 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 975379 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 15665 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12168 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 701708 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 624080 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1325788 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 862427395 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 24732275 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1885785 # Number of squashed instructions skipped in execute
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iew.exec_refs 33921373 # number of memory reference insts executed
system.cpu.iew.exec_branches 86494176 # Number of branches executed
system.cpu.iew.exec_stores 9189098 # Number of stores executed
system.cpu.iew.exec_rate 1.822454 # Inst execution rate
system.cpu.iew.wb_sent 861944484 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 853917813 # cumulative count of insts written-back
system.cpu.iew.wb_producers 669630870 # num instructions producing a value
system.cpu.iew.wb_consumers 1918703675 # num instructions consuming a value
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iew.wb_rate 1.804472 # insts written-back per cycle
Regression: Update stats due to changes to x86 cpuid instruction
2012-07-23 03:31:24 +02:00
system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.commitCommittedInsts 426513995 # The number of committed instructions
system.cpu.commit.commitCommittedOps 840512563 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26872606 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1515656 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1183314 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 306215725 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.744838 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.861126 # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.committed_per_cycle::0 125266635 40.91% 40.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14734551 4.81% 45.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4258737 1.39% 47.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 76646765 25.03% 72.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3892941 1.27% 73.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1792387 0.59% 74.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1104205 0.36% 74.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71994718 23.51% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6524786 2.13% 100.00% # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.committed_per_cycle::total 306215725 # Number of insts commited each cycle
system.cpu.commit.committedInsts 426513995 # Number of instructions committed
system.cpu.commit.committedOps 840512563 # Number of ops (including micro ops) committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.refs 23694211 # Number of memory references committed
system.cpu.commit.loads 15292077 # Number of loads committed
system.cpu.commit.membars 781571 # Number of memory barriers committed
system.cpu.commit.branches 85505598 # Number of branches committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.int_insts 768332766 # Number of committed integer instructions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.commit.bw_lim_events 6524786 # number cycles where commit BW limit reached
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.rob.rob_reads 1166996622 # The number of ROB reads
system.cpu.rob.rob_writes 1738897212 # The number of ROB writes
system.cpu.timesIdled 2997983 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 162910091 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9872594876 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 426513995 # Number of Instructions Simulated
system.cpu.committedOps 840512563 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 426513995 # Number of Instructions Simulated
system.cpu.cpi 1.109514 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.109514 # CPI: Total CPI of All Threads
system.cpu.ipc 0.901296 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.901296 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2163164515 # number of integer regfile reads
system.cpu.int_regfile_writes 1362660599 # number of integer regfile writes
system.cpu.fp_regfile_reads 96 # number of floating regfile reads
system.cpu.misc_regfile_reads 281055752 # number of misc regfile reads
system.cpu.misc_regfile_writes 403699 # number of misc regfile writes
system.cpu.icache.replacements 1072786 # number of replacements
system.cpu.icache.tagsinuse 510.225454 # Cycle average of tags in use
system.cpu.icache.total_refs 8218240 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1073298 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.656997 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 56932893000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.225454 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996534 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996534 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 8218240 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8218240 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8218240 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8218240 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8218240 # number of overall hits
system.cpu.icache.overall_hits::total 8218240 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1144801 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1144801 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1144801 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1144801 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1144801 # number of overall misses
system.cpu.icache.overall_misses::total 1144801 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18871083485 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18871083485 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18871083485 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18871083485 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18871083485 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18871083485 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9363041 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9363041 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9363041 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9363041 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9363041 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9363041 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122268 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.122268 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.122268 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.122268 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.122268 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.122268 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16484.160553 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16484.160553 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3261491 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.icache.blocked::no_mshrs 378 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 8628.283069 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69972 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 69972 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 69972 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 69972 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 69972 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 69972 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074829 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1074829 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1074829 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1074829 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1074829 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1074829 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14733142991 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14733142991 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14733142991 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14733142991 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14733142991 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14733142991 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114795 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.114795 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.114795 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.itb_walker_cache.replacements 11223 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.037503 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 31260 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 11237 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.781881 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5131387386000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.037503 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377344 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.377344 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31468 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 31468 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31471 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 31471 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31471 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 31471 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12107 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 12107 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12107 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 12107 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12107 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 12107 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 196957000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 196957000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 196957000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 196957000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 196957000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 196957000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43575 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 43575 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43578 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 43578 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43578 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 43578 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.277843 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.277843 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.277824 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.277824 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.277824 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.277824 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 1700 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1700 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12107 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12107 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12107 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 12107 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12107 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 12107 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159950045 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159950045 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159950045 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159950045 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159950045 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159950045 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.277843 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.277843 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.277824 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.277824 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dtb_walker_cache.replacements 118986 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 13.873264 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 132191 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 119002 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.110830 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5112880781000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.873264 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.867079 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.867079 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 132191 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 132191 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 132191 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 132191 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 132191 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 132191 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 120057 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 120057 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 120057 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 120057 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 120057 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 120057 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2156991000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2156991000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2156991000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 2156991000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2156991000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 2156991000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 252248 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 252248 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 252248 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 252248 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 252248 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 252248 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.475948 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.475948 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.475948 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.475948 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.475948 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.475948 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 34205 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 34205 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 120057 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 120057 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 120057 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 120057 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 120057 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 120057 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1794187508 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1794187508 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1794187508 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.475948 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.475948 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.475948 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dcache.replacements 1672900 # number of replacements
system.cpu.dcache.tagsinuse 511.996980 # Cycle average of tags in use
system.cpu.dcache.total_refs 19011613 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1673412 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.360988 # Average number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit.
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dcache.occ_blocks::cpu.data 511.996980 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10933058 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10933058 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8074504 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8074504 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19007562 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19007562 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19007562 # number of overall hits
system.cpu.dcache.overall_hits::total 19007562 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2431156 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2431156 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 318255 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 318255 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2749411 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2749411 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2749411 # number of overall misses
system.cpu.dcache.overall_misses::total 2749411 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 45213675500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 45213675500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10676522982 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10676522982 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 55890198482 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 55890198482 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 55890198482 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 55890198482 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13364214 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13364214 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8392759 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8392759 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21756973 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21756973 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21756973 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21756973 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181915 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.181915 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037920 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037920 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.126369 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.126369 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.126369 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.126369 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18597.603568 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18597.603568 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33547.070689 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33547.070689 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20328.062440 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20328.062440 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 26730982 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dcache.blocked::no_mshrs 4911 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5443.083282 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.dcache.writebacks::writebacks 1571690 # number of writebacks
system.cpu.dcache.writebacks::total 1571690 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049439 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1049439 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22786 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 22786 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1072225 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1072225 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1072225 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1072225 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381717 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1381717 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295469 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 295469 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1677186 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1677186 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1677186 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1677186 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23302977034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23302977034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9408800483 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9408800483 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32711777517 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32711777517 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32711777517 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32711777517 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208357000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208357000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386111000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386111000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594468000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594468000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103389 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103389 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035205 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035205 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077087 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077087 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink