2006-06-28 17:02:14 +02:00
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/*
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2015-03-27 09:55:55 +01:00
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* Copyright (c) 2012-2013, 2015 ARM Limited
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2012-11-02 17:32:02 +01:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-06-28 17:02:14 +02:00
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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2012-11-02 17:32:02 +01:00
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* Andreas Sandberg
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2006-06-28 17:02:14 +02:00
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*/
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/** @file
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* Declaration of a structure to manage MSHRs.
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*/
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2015-03-27 09:55:55 +01:00
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#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
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#define __MEM_CACHE_MSHR_QUEUE_HH__
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2006-06-28 17:02:14 +02:00
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#include <vector>
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2007-06-18 02:27:53 +02:00
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2008-02-10 23:45:25 +01:00
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#include "mem/cache/mshr.hh"
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2011-04-15 19:44:06 +02:00
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#include "mem/packet.hh"
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2012-11-02 17:32:02 +01:00
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#include "sim/drain.hh"
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2006-06-28 17:02:14 +02:00
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/**
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2006-10-23 05:38:34 +02:00
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* A Class for maintaining a list of pending and allocated memory requests.
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2006-06-28 17:02:14 +02:00
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*/
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2012-11-02 17:32:02 +01:00
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class MSHRQueue : public Drainable
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2007-06-18 02:27:53 +02:00
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{
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2006-06-28 17:02:14 +02:00
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private:
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2008-01-02 21:20:15 +01:00
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/** Local label (for functional print requests) */
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const std::string label;
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2006-06-28 17:02:14 +02:00
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// Parameters
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/**
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2007-06-18 02:27:53 +02:00
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* The total number of entries in this queue. This number is set as the
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* number of entries requested plus (numReserve - 1). This allows for
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* the same number of effective entries while still maintaining the reserve.
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2006-06-28 17:02:14 +02:00
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*/
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2007-06-18 02:27:53 +02:00
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const int numEntries;
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* The number of entries to hold in reserve. This is needed because copy
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* operations can allocate upto 4 entries at one time.
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2006-06-28 17:02:14 +02:00
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*/
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const int numReserve;
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2014-12-23 15:31:18 +01:00
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/**
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* The number of entries to reserve for future demand accesses.
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* Prevent prefetcher from taking all mshr entries
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*/
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const int demandReserve;
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2013-05-30 18:54:11 +02:00
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/** MSHR storage. */
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std::vector<MSHR> registers;
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/** Holds pointers to all allocated entries. */
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MSHR::List allocatedList;
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/** Holds pointers to entries that haven't been sent to the bus. */
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MSHR::List readyList;
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/** Holds non allocated entries. */
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MSHR::List freeList;
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2007-06-25 15:47:05 +02:00
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MSHR::Iterator addToReadyList(MSHR *mshr);
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2006-06-28 17:02:14 +02:00
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public:
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2007-06-18 02:27:53 +02:00
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/** The number of allocated entries. */
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2006-06-28 17:02:14 +02:00
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int allocated;
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2007-06-18 02:27:53 +02:00
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/** The number of entries that have been forwarded to the bus. */
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int inServiceEntries;
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2007-06-21 20:59:17 +02:00
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/** The index of this queue within the cache (MSHR queue vs. write
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* buffer). */
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const int index;
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Create a queue with a given number of entries.
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* @param num_entrys The number of entries in this queue.
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* @param reserve The minimum number of entries needed to satisfy
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* any access.
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2014-12-23 15:31:18 +01:00
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* @param demand_reserve The minimum number of entries needed to satisfy
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* demand accesses.
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2006-06-28 17:02:14 +02:00
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*/
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2008-01-02 21:20:15 +01:00
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MSHRQueue(const std::string &_label, int num_entries, int reserve,
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2014-12-23 15:31:18 +01:00
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int demand_reserve, int index);
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Find the first MSHR that matches the provided address.
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2015-03-27 09:55:55 +01:00
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* @param blk_addr The block address to find.
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2014-01-24 22:29:30 +01:00
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* @param is_secure True if the target memory space is secure.
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2006-06-28 17:02:14 +02:00
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* @return Pointer to the matching MSHR, null if not found.
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*/
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2015-03-27 09:55:55 +01:00
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MSHR *findMatch(Addr blk_addr, bool is_secure) const;
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Find and return all the matching entries in the provided vector.
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2015-03-27 09:55:55 +01:00
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* @param blk_addr The block address to find.
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2014-01-24 22:29:30 +01:00
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* @param is_secure True if the target memory space is secure.
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2007-06-18 02:27:53 +02:00
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* @param matches The vector to return pointers to the matching entries.
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2006-06-28 17:02:14 +02:00
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* @return True if any matches are found, false otherwise.
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*/
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2015-03-27 09:55:55 +01:00
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bool findMatches(Addr blk_addr, bool is_secure,
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2014-01-24 22:29:30 +01:00
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std::vector<MSHR*>& matches) const;
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2006-06-28 17:02:14 +02:00
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/**
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2006-10-23 05:38:34 +02:00
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* Find any pending requests that overlap the given request.
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2015-03-27 09:55:55 +01:00
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* @param blk_addr Block address.
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2014-01-24 22:29:30 +01:00
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* @param is_secure True if the target memory space is secure.
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2006-06-28 17:02:14 +02:00
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* @return A pointer to the earliest matching MSHR.
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*/
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2015-03-27 09:55:55 +01:00
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MSHR *findPending(Addr blk_addr, bool is_secure) const;
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2006-06-28 17:02:14 +02:00
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2007-07-27 21:46:45 +02:00
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bool checkFunctional(PacketPtr pkt, Addr blk_addr);
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2006-06-28 17:02:14 +02:00
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/**
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2006-10-23 05:38:34 +02:00
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* Allocates a new MSHR for the request and size. This places the request
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2006-06-28 17:02:14 +02:00
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* as the first target in the MSHR.
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2015-03-27 09:55:55 +01:00
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*
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* @param blk_addr The address of the block.
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* @param blk_size The number of bytes to request.
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* @param pkt The original miss.
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* @param when_ready When should the MSHR be ready to act upon.
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* @param order The logical order of this MSHR
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mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.
The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.
This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.
Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.
The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
2015-11-06 09:26:41 +01:00
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* @param alloc_on_fill Should the cache allocate a block on fill
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2015-03-27 09:55:55 +01:00
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*
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2006-06-28 17:02:14 +02:00
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* @return The a pointer to the MSHR allocated.
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*
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2007-06-18 02:27:53 +02:00
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* @pre There are free entries.
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2006-06-28 17:02:14 +02:00
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*/
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2015-03-27 09:55:55 +01:00
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MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
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mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.
The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.
This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.
Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.
The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
2015-11-06 09:26:41 +01:00
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Tick when_ready, Counter order, bool alloc_on_fill);
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2006-06-28 17:02:14 +02:00
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/**
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* Removes the given MSHR from the queue. This places the MSHR on the
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* free list.
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* @param mshr
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*/
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2007-06-18 02:27:53 +02:00
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void deallocate(MSHR *mshr);
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Remove a MSHR from the queue. Returns an iterator into the
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2015-12-28 17:14:16 +01:00
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* allocatedList.
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2006-06-28 17:02:14 +02:00
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* @param mshr The MSHR to remove.
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* @return An iterator to the next entry in the allocatedList.
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*/
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2007-06-18 02:27:53 +02:00
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MSHR::Iterator deallocateOne(MSHR *mshr);
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Moves the MSHR to the front of the pending list if it is not
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* in service.
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* @param mshr The entry to move.
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2006-06-28 17:02:14 +02:00
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*/
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void moveToFront(MSHR *mshr);
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/**
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* Mark the given MSHR as in service. This removes the MSHR from the
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2015-02-03 20:25:59 +01:00
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* readyList or deallocates the MSHR if it does not expect a response.
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*
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2006-06-28 17:02:14 +02:00
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* @param mshr The MSHR to mark in service.
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2015-02-03 20:25:59 +01:00
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* @param pending_dirty_resp Whether we expect a dirty response
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* from another cache
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2006-06-28 17:02:14 +02:00
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*/
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2015-02-03 20:25:59 +01:00
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void markInService(MSHR *mshr, bool pending_dirty_resp);
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-18 02:27:53 +02:00
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* Mark an in service entry as pending, used to resend a request.
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2006-06-28 17:02:14 +02:00
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* @param mshr The MSHR to resend.
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*/
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2007-06-18 02:27:53 +02:00
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void markPending(MSHR *mshr);
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2006-06-28 17:02:14 +02:00
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2014-05-10 00:58:46 +02:00
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/**
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* Deallocate top target, possibly freeing the MSHR
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* @return if MSHR queue is no longer full
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*/
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bool forceDeallocateTarget(MSHR *mshr);
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2006-06-28 17:02:14 +02:00
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/**
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* Returns true if the pending list is not empty.
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2006-10-23 05:38:34 +02:00
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* @return True if there are outstanding requests.
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2006-06-28 17:02:14 +02:00
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*/
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bool havePending() const
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{
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2007-06-25 15:47:05 +02:00
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return !readyList.empty();
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2006-06-28 17:02:14 +02:00
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}
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/**
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2007-06-18 02:27:53 +02:00
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* Returns true if there are no free entries.
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2006-06-28 17:02:14 +02:00
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* @return True if this queue is full.
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*/
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bool isFull() const
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{
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2007-06-18 02:27:53 +02:00
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return (allocated > numEntries - numReserve);
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2006-06-28 17:02:14 +02:00
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}
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2014-12-23 15:31:18 +01:00
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/**
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* Returns true if sufficient mshrs for prefetch.
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* @return True if sufficient mshrs for prefetch.
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*/
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bool canPrefetch() const
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{
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return (allocated < numEntries - (numReserve + demandReserve));
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}
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2006-06-28 17:02:14 +02:00
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/**
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2007-06-25 15:47:05 +02:00
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* Returns the MSHR at the head of the readyList.
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2006-10-23 05:38:34 +02:00
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* @return The next request to service.
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2006-06-28 17:02:14 +02:00
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*/
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2007-06-18 02:27:53 +02:00
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MSHR *getNextMSHR() const
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2006-06-28 17:02:14 +02:00
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{
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2011-01-08 06:50:29 +01:00
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if (readyList.empty() || readyList.front()->readyTime > curTick()) {
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2006-06-28 17:02:14 +02:00
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return NULL;
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}
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2007-06-25 15:47:05 +02:00
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return readyList.front();
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}
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2007-06-30 22:34:16 +02:00
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Tick nextMSHRReadyTime() const
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2007-06-25 15:47:05 +02:00
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{
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2007-06-30 22:34:16 +02:00
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return readyList.empty() ? MaxTick : readyList.front()->readyTime;
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2006-06-28 17:02:14 +02:00
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}
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2012-11-02 17:32:02 +01:00
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2015-10-12 10:07:59 +02:00
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DrainState drain() override;
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2006-06-28 17:02:14 +02:00
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};
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2015-03-27 09:55:55 +01:00
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#endif //__MEM_CACHE_MSHR_QUEUE_HH__
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