gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.962058                       # Number of seconds simulated
sim_ticks                                1962057812000                       # Number of ticks simulated
final_tick                               1962057812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1235183                       # Simulator instruction rate (inst/s)
host_op_rate                                  1235183                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            40819911602                       # Simulator tick rate (ticks/s)
host_mem_usage                                 297060                       # Number of bytes of host memory used
host_seconds                                    48.07                       # Real time elapsed on the host
sim_insts                                    59370518                       # Number of instructions simulated
sim_ops                                      59370518                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           834432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24593280                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            29312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           572992                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28680832                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       834432                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        29312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          863744                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7715456                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7715456                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13038                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            384270                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               458                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8953                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                448138                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120554                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120554                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              425284                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12534432                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1351039                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               14939                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              292036                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14617730                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         425284                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          14939                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440224                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3932329                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3932329                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3932329                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             425284                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12534432                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1351039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              14939                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             292036                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18550059                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        341238                       # number of replacements
system.l2c.tagsinuse                     65290.171288                       # Cycle average of tags in use
system.l2c.total_refs                         2492514                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        406253                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.135374                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    7854344000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        55481.148199                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4824.640956                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          4855.323185                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           116.032373                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            13.026576                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.846575                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.073618                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.074086                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.001771                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000199                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996249                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             902430                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             773977                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              86748                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              31919                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1795074                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          820361                       # number of Writeback hits
system.l2c.Writeback_hits::total               820361                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             161                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              57                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 218                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            21                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            21                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                42                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           172410                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            12341                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               184751                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              902430                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              946387                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               86748                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               44260                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1979825                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             902430                       # number of overall hits
system.l2c.overall_hits::cpu0.data             946387                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              86748                       # number of overall hits
system.l2c.overall_hits::cpu1.data              44260                       # number of overall hits
system.l2c.overall_hits::total                1979825                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13038                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           271462                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              469                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              326                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285295                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2435                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           490                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2925                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           34                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           73                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             107                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         113176                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8669                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121845                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13038                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            384638                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               469                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8995                       # number of demand (read+write) misses
system.l2c.demand_misses::total                407140                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13038                       # number of overall misses
system.l2c.overall_misses::cpu0.data           384638                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              469                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8995                       # number of overall misses
system.l2c.overall_misses::total               407140                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    678189500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14120883000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     24328000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     17368000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    14840768500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1412000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1560000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2972000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       156000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       364000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5885512000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    450808000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6336320000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    678189500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20006395000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     24328000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    468176000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21177088500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    678189500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20006395000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     24328000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    468176000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21177088500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         915468                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1045439                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          87217                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          32245                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2080369                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       820361                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           820361                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2596                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          547                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3143                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           55                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           94                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           149                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       285586                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        21010                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           306596                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          915468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1331025                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           87217                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           53255                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2386965                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         915468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1331025                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          87217                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          53255                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2386965                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014242                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.259663                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.005377                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.010110                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.137137                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.937982                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.895795                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.930640                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.618182                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.776596                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.718121                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.396294                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.412613                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.397412                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014242                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.288979                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005377                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.168904                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.170568                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014242                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.288979                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005377                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.168904                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.170568                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52019.027673                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   579.876797                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3183.673469                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1016.068376                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4588.235294                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2849.315068                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3401.869159                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52003.118716                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52014.266591                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52014.266591                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79034                       # number of writebacks
system.l2c.writebacks::total                    79034                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13038                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       271462                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          458                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          326                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285284                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2435                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          490                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2925                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           34                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           73                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          107                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       113176                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8669                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121845                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13038                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       384638                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          458                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8995                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           407129                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13038                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       384638                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          458                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8995                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          407129                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    521730000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10863339000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     18343000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     13456000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11416868000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     97460000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19615000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    117075000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1360000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2920000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4280000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4527400000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    346780000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4874180000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    521730000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15390739000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     18343000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    360236000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16291048000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    521730000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15390739000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     18343000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    360236000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16291048000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1369455000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     19250000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1388705000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1966544000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    505236000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2471780000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3335999000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    524486000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3860485000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014242                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259663                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005251                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010110                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.137131                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.937982                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.895795                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.930640                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.618182                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.776596                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.718121                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.396294                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.412613                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.397412                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014242                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.288979                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005251                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.168904                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.170563                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014242                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.288979                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005251                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.168904                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.170563                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40016.106765                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.899374                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.218341                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41276.073620                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.307076                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.640657                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.612245                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.641026                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.118716                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40016.106765                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.568602                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40014.462247                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40014.462247                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41698                       # number of replacements
system.iocache.tagsinuse                     0.566822                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1754521474000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.566822                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.035426                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.035426                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
system.iocache.overall_misses::total            41730                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21239998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21239998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  11448106806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11448106806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  11469346804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11469346804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  11469346804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11469346804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119325.831461                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 275512.774499                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 274846.556530                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 274846.556530                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs     199371000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                24657                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  8085.776858                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11983000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11983000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   9287247000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   9287247000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   9299230000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9299230000                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   9299230000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9299230000                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 222842.798946                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 222842.798946                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8658368                       # DTB read hits
system.cpu0.dtb.read_misses                      7687                       # DTB read misses
system.cpu0.dtb.read_acv                          174                       # DTB read access violations
system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
system.cpu0.dtb.write_hits                    6036843                       # DTB write hits
system.cpu0.dtb.write_misses                      798                       # DTB write misses
system.cpu0.dtb.write_acv                         115                       # DTB write access violations
system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
system.cpu0.dtb.data_hits                    14695211                       # DTB hits
system.cpu0.dtb.data_misses                      8485                       # DTB misses
system.cpu0.dtb.data_acv                          289                       # DTB access violations
system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
system.cpu0.itb.fetch_hits                    3948323                       # ITB hits
system.cpu0.itb.fetch_misses                     3841                       # ITB misses
system.cpu0.itb.fetch_acv                         143                       # ITB acv
system.cpu0.itb.fetch_accesses                3952164                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3924115624                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   54116505                       # Number of instructions committed
system.cpu0.committedOps                     54116505                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             50087098                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                302903                       # Number of float alu accesses
system.cpu0.num_func_calls                    1426970                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      6243728                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    50087098                       # number of integer instructions
system.cpu0.num_fp_insts                       302903                       # number of float instructions
system.cpu0.num_int_register_reads           68610814                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          37122288                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              149298                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             152355                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     14741096                       # number of memory refs
system.cpu0.num_load_insts                    8689646                       # Number of load instructions
system.cpu0.num_store_insts                   6051450                       # Number of store instructions
system.cpu0.num_idle_cycles              3676817171.998126                       # Number of idle cycles
system.cpu0.num_busy_cycles              247298452.001874                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.063020                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.936980                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    202757                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   72604     40.61%     40.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.07%     40.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1979      1.11%     41.79% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 104050     58.20%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              178770                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    71235     49.27%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1979      1.37%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   71229     49.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               144580                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1900688314000     96.87%     96.87% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21              102511500      0.01%     96.88% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              795126500      0.04%     96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                5572000      0.00%     96.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            60465450000      3.08%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1962056974000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981144                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684565                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808749                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         6      2.68%      2.68% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.48%     11.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.34%     12.50% # number of syscalls executed
system.cpu0.kern.syscall::6                        30     13.39%     25.89% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     26.34% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.45%     26.79% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.46%     31.25% # number of syscalls executed
system.cpu0.kern.syscall::19                        6      2.68%     33.93% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.79%     35.71% # number of syscalls executed
system.cpu0.kern.syscall::23                        2      0.89%     36.61% # number of syscalls executed
system.cpu0.kern.syscall::24                        4      1.79%     38.39% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.57%     41.96% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.89%     42.86% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     17.41%     60.27% # number of syscalls executed
system.cpu0.kern.syscall::47                        4      1.79%     62.05% # number of syscalls executed
system.cpu0.kern.syscall::48                        7      3.12%     65.18% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.02%     69.20% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     69.64% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.23%     71.88% # number of syscalls executed
system.cpu0.kern.syscall::71                       32     14.29%     86.16% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.34%     87.50% # number of syscalls executed
system.cpu0.kern.syscall::74                        9      4.02%     91.52% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     91.96% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.89%     92.86% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.12%     95.98% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.89%     96.87% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.89%     97.77% # number of syscalls executed
system.cpu0.kern.syscall::132                       2      0.89%     98.66% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.45%     99.11% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   224                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                   91      0.05%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3872      2.06%      2.11% # number of callpals executed
system.cpu0.kern.callpal::tbi                      44      0.02%      2.13% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
system.cpu0.kern.callpal::swpipl               171948     91.52%     93.66% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6691      3.56%     97.22% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     97.22% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     7      0.00%     97.23% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.23% # number of callpals executed
system.cpu0.kern.callpal::rti                    4705      2.50%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 356      0.19%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     149      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                187881                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7233                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1235                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1234                      
system.cpu0.kern.mode_good::user                 1235                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.170607                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.291568                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1958395542000     99.81%     99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3661425000      0.19%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3873                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                914851                       # number of replacements
system.cpu0.icache.tagsinuse               508.781994                       # Cycle average of tags in use
system.cpu0.icache.total_refs                53209789                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                915362                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 58.129777                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           36528993000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   508.781994                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.993715                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.993715                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     53209789                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       53209789                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     53209789                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        53209789                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     53209789                       # number of overall hits
system.cpu0.icache.overall_hits::total       53209789                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       915491                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       915491                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       915491                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        915491                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       915491                       # number of overall misses
system.cpu0.icache.overall_misses::total       915491                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13646549000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13646549000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13646549000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13646549000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13646549000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13646549000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     54125280                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     54125280                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     54125280                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     54125280                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     54125280                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     54125280                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016914                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.016914                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016914                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.016914                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016914                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.016914                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14906.262323                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14906.262323                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915491                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       915491                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       915491                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       915491                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       915491                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       915491                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10899382500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10899382500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10899382500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10899382500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10899382500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10899382500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016914                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016914                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016914                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.016914                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016914                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.016914                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1337819                       # number of replacements
system.cpu0.dcache.tagsinuse               506.532892                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13370103                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1338331                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.990132                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle             101834000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   506.532892                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.989322                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.989322                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7444463                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7444463                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5554933                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5554933                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       175817                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       175817                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191182                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       191182                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12999396                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12999396                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12999396                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12999396                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1037635                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1037635                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       289296                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       289296                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16772                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        16772                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          445                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          445                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1326931                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1326931                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1326931                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1326931                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  26113637000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  26113637000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8963228000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8963228000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    238633000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    238633000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4867000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      4867000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  35076865000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  35076865000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  35076865000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  35076865000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8482098                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8482098                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5844229                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5844229                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       192589                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       192589                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       191627                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       191627                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14326327                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14326327                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14326327                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14326327                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122332                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.122332                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049501                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.049501                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.087087                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.087087                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002322                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002322                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092622                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.092622                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092622                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.092622                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       785166                       # number of writebacks
system.cpu0.dcache.writebacks::total           785166                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1037635                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1037635                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       289296                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       289296                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16772                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16772                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          445                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          445                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1326931                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1326931                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1326931                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1326931                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23000669022                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23000669022                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8095339001                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8095339001                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    188317000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    188317000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3531001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3531001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  31096008023                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  31096008023                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  31096008023                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  31096008023                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1461823000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1461823000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2088243000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2088243000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3550066000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3550066000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122332                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122332                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049501                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049501                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087087                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087087                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092622                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092622                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092622                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092622                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7934.833708                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7934.833708                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1027530                       # DTB read hits
system.cpu1.dtb.read_misses                      2750                       # DTB read misses
system.cpu1.dtb.read_acv                           36                       # DTB read access violations
system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
system.cpu1.dtb.write_hits                     663193                       # DTB write hits
system.cpu1.dtb.write_misses                      356                       # DTB write misses
system.cpu1.dtb.write_acv                          48                       # DTB write access violations
system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
system.cpu1.dtb.data_hits                     1690723                       # DTB hits
system.cpu1.dtb.data_misses                      3106                       # DTB misses
system.cpu1.dtb.data_acv                           84                       # DTB access violations
system.cpu1.dtb.data_accesses                  302878                       # DTB accesses
system.cpu1.itb.fetch_hits                    1394871                       # ITB hits
system.cpu1.itb.fetch_misses                     1246                       # ITB misses
system.cpu1.itb.fetch_acv                          41                       # ITB acv
system.cpu1.itb.fetch_accesses                1396117                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3923836552                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    5254013                       # Number of instructions committed
system.cpu1.committedOps                      5254013                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              4921025                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 25430                       # Number of float alu accesses
system.cpu1.num_func_calls                     157600                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       506865                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     4921025                       # number of integer instructions
system.cpu1.num_fp_insts                        25430                       # number of float instructions
system.cpu1.num_int_register_reads            6827399                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           3700117                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               16282                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              16129                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      1700348                       # number of memory refs
system.cpu1.num_load_insts                    1033584                       # Number of load instructions
system.cpu1.num_store_insts                    666764                       # Number of store instructions
system.cpu1.num_idle_cycles              3903107404.303190                       # Number of idle cycles
system.cpu1.num_busy_cycles              20729147.696810                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.005283                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.994717                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2331                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     35942                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                    9143     31.85%     31.85% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1973      6.87%     38.72% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                     91      0.32%     39.04% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  17499     60.96%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               28706                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                     9135     45.13%     45.13% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1973      9.75%     54.87% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                      91      0.45%     55.32% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                    9044     44.68%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                20243                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1920766593500     97.90%     97.90% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              726074500      0.04%     97.94% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               67017000      0.00%     97.94% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            40358561000      2.06%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1961918246000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.999125                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.516830                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.705184                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         2      1.96%      1.96% # number of syscalls executed
system.cpu1.kern.syscall::3                        11     10.78%     12.75% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.98%     13.73% # number of syscalls executed
system.cpu1.kern.syscall::6                        12     11.76%     25.49% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      4.90%     30.39% # number of syscalls executed
system.cpu1.kern.syscall::19                        4      3.92%     34.31% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.96%     36.27% # number of syscalls executed
system.cpu1.kern.syscall::23                        2      1.96%     38.24% # number of syscalls executed
system.cpu1.kern.syscall::24                        2      1.96%     40.20% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      2.94%     43.14% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     14.71%     57.84% # number of syscalls executed
system.cpu1.kern.syscall::47                        2      1.96%     59.80% # number of syscalls executed
system.cpu1.kern.syscall::48                        3      2.94%     62.75% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.98%     63.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.96%     65.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       22     21.57%     87.25% # number of syscalls executed
system.cpu1.kern.syscall::74                        7      6.86%     94.12% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.98%     95.10% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.96%     97.06% # number of syscalls executed
system.cpu1.kern.syscall::132                       2      1.96%     99.02% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.98%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   102                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  365      1.24%      1.27% # number of callpals executed
system.cpu1.kern.callpal::tbi                      10      0.03%      1.31% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.33% # number of callpals executed
system.cpu1.kern.callpal::swpipl                24054     81.82%     83.15% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2165      7.36%     90.51% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.52% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.01%     90.53% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     2      0.01%     90.53% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     90.54% # number of callpals executed
system.cpu1.kern.callpal::rti                    2587      8.80%     99.34% # number of callpals executed
system.cpu1.kern.callpal::callsys                 161      0.55%     99.89% # number of callpals executed
system.cpu1.kern.callpal::imb                      31      0.11%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 29399                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              879                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                515                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2075                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                531                      
system.cpu1.kern.mode_good::user                  515                      
system.cpu1.kern.mode_good::idle                   16                      
system.cpu1.kern.mode_switch_good::kernel     0.604096                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.007711                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.306140                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        4075179000      0.21%      0.21% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1593973000      0.08%      0.29% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1955466537000     99.71%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     366                       # number of times the context was actually changed
system.cpu1.icache.replacements                 86678                       # number of replacements
system.cpu1.icache.tagsinuse               419.761864                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5169985                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                 87190                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 59.295619                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1958463060000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   419.761864                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.819847                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.819847                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      5169985                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        5169985                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      5169985                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         5169985                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      5169985                       # number of overall hits
system.cpu1.icache.overall_hits::total        5169985                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst        87218                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total        87218                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst        87218                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total         87218                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst        87218                       # number of overall misses
system.cpu1.icache.overall_misses::total        87218                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1315004000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1315004000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1315004000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1315004000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1315004000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1315004000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      5257203                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      5257203                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      5257203                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      5257203                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      5257203                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      5257203                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016590                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.016590                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016590                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.016590                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016590                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.016590                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15077.208833                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15077.208833                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        87218                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total        87218                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst        87218                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total        87218                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst        87218                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total        87218                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1053316500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   1053316500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1053316500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   1053316500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1053316500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   1053316500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016590                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.016590                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.016590                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 53530                       # number of replacements
system.cpu1.dcache.tagsinuse               416.811223                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1627239                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 53938                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 30.168694                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1941569871000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   416.811223                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.814084                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.814084                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data       982758                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total         982758                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       626472                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        626472                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11310                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        11310                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11707                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        11707                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1609230                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1609230                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1609230                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1609230                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data        35626                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        35626                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        22614                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        22614                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1003                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1003                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          544                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          544                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data        58240                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total         58240                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data        58240                       # number of overall misses
system.cpu1.dcache.overall_misses::total        58240                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    484494000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total    484494000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    694414000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total    694414000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     12192000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     12192000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      7087000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      7087000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   1178908000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   1178908000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   1178908000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   1178908000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1018384                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1018384                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       649086                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       649086                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        12313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12251                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        12251                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1667470                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1667470                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1667470                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1667470                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.034983                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.034983                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034840                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.034840                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081459                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.081459                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044405                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.044405                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034927                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.034927                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034927                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.034927                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        35195                       # number of writebacks
system.cpu1.dcache.writebacks::total            35195                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        35626                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        35626                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        22614                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        22614                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1003                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1003                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          544                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          544                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        58240                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        58240                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        58240                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        58240                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    377607005                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    377607005                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    626568004                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    626568004                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9183000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      9183000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5455000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5455000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1004175009                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1004175009                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1004175009                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1004175009                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     20565000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     20565000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    534647000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    534647000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    555212000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    555212000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.034983                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.034983                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034840                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034840                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.081459                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.081459                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.044405                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.044405                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034927                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.034927                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034927                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034927                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9155.533400                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9155.533400                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------