2009-07-09 08:02:20 +02:00
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/*
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2010-06-02 19:57:59 +02:00
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2009-07-09 08:02:20 +02:00
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_MRM_ISA_HH__
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2009-07-10 05:28:27 +02:00
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#include "arch/arm/registers.hh"
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2009-07-09 08:02:20 +02:00
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#include "arch/arm/types.hh"
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2009-07-10 05:28:27 +02:00
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class ThreadContext;
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2009-07-09 08:02:20 +02:00
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA
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{
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protected:
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2009-07-10 05:28:27 +02:00
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MiscReg miscRegs[NumMiscRegs];
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2009-11-08 09:07:49 +01:00
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const IntRegIndex *intRegMap;
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void
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updateRegMap(CPSR cpsr)
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{
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switch (cpsr.mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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intRegMap = IntRegUsrMap;
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break;
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case MODE_FIQ:
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intRegMap = IntRegFiqMap;
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break;
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case MODE_IRQ:
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intRegMap = IntRegIrqMap;
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break;
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case MODE_SVC:
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intRegMap = IntRegSvcMap;
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break;
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2009-11-08 11:01:02 +01:00
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case MODE_MON:
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intRegMap = IntRegMonMap;
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break;
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2009-11-08 09:07:49 +01:00
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case MODE_ABORT:
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intRegMap = IntRegAbtMap;
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break;
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case MODE_UNDEFINED:
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intRegMap = IntRegUndMap;
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break;
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default:
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panic("Unrecognized mode setting in CPSR.\n");
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}
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}
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2009-07-09 08:02:20 +02:00
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public:
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2009-07-10 05:28:27 +02:00
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void clear()
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{
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2009-07-27 09:52:48 +02:00
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memset(miscRegs, 0, sizeof(miscRegs));
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CPSR cpsr = 0;
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2009-11-08 09:54:32 +01:00
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cpsr.mode = MODE_USER;
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2009-07-27 09:52:48 +02:00
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miscRegs[MISCREG_CPSR] = cpsr;
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2009-11-08 09:07:49 +01:00
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updateRegMap(cpsr);
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2009-11-11 05:34:38 +01:00
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SCTLR sctlr = 0;
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sctlr.nmfi = 1;
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sctlr.rao1 = 1;
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sctlr.rao2 = 1;
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sctlr.rao3 = 1;
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sctlr.rao4 = 1;
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2010-06-02 19:58:08 +02:00
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miscRegs[MISCREG_SCTLR] = sctlr;
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2009-11-11 05:34:38 +01:00
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2010-06-02 19:58:09 +02:00
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/*
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* Technically this should be 0, but we don't support those
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* settings.
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*/
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2010-06-02 19:58:11 +02:00
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CPACR cpacr = 0;
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// Enable CP 10, 11
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cpacr.cp10 = 0x3;
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cpacr.cp11 = 0x3;
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miscRegs[MISCREG_CPACR] = cpacr;
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2010-06-02 19:58:09 +02:00
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2010-06-02 19:58:13 +02:00
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/* Start with an event in the mailbox */
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miscRegs[MISCREG_SEV_MAILBOX] = 1;
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2010-06-02 19:58:10 +02:00
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/*
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* Implemented = '5' from "M5",
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* Variant = 0,
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*/
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miscRegs[MISCREG_MIDR] =
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(0x35 << 24) | //Implementor is '5' from "M5"
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(0 << 20) | //Variant
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(0xf << 16) | //Architecture from CPUID scheme
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(0 << 4) | //Primary part number
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(0 << 0) | //Revision
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0;
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2010-06-02 19:58:13 +02:00
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// Separate Instruction and Data TLBs.
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miscRegs[MISCREG_TLBTR] = 1;
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2009-07-27 09:52:48 +02:00
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//XXX We need to initialize the rest of the state.
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2009-07-10 05:28:27 +02:00
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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2009-11-15 04:22:29 +01:00
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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return miscRegs[MISCREG_SPSR];
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case MODE_FIQ:
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return miscRegs[MISCREG_SPSR_FIQ];
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case MODE_IRQ:
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return miscRegs[MISCREG_SPSR_IRQ];
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case MODE_SVC:
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return miscRegs[MISCREG_SPSR_SVC];
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case MODE_MON:
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return miscRegs[MISCREG_SPSR_MON];
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case MODE_ABORT:
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return miscRegs[MISCREG_SPSR_ABT];
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case MODE_UNDEFINED:
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return miscRegs[MISCREG_SPSR_UND];
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default:
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return miscRegs[MISCREG_SPSR];
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}
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}
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2009-07-10 05:28:27 +02:00
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return miscRegs[misc_reg];
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}
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MiscReg
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readMiscReg(int misc_reg, ThreadContext *tc)
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{
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2010-06-02 19:57:59 +02:00
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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Addr pc = tc->readPC();
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if (pc & (ULL(1) << PcJBitShift))
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cpsr.j = 1;
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else
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cpsr.j = 0;
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if (pc & (ULL(1) << PcTBitShift))
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cpsr.t = 1;
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else
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cpsr.t = 0;
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return cpsr;
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}
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2010-06-02 19:58:08 +02:00
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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2010-06-02 19:58:09 +02:00
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switch (misc_reg) {
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case MISCREG_CLIDR:
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warn("The clidr register always reports 0 caches.\n");
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break;
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2010-06-02 19:58:09 +02:00
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case MISCREG_CCSIDR:
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warn("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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2010-06-02 19:58:09 +02:00
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}
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2009-11-15 04:22:29 +01:00
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return readMiscRegNoEffect(misc_reg);
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2009-07-10 05:28:27 +02:00
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}
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2009-07-09 08:02:20 +02:00
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2009-07-10 05:28:27 +02:00
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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2009-11-15 04:22:29 +01:00
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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miscRegs[MISCREG_SPSR] = val;
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return;
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case MODE_FIQ:
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miscRegs[MISCREG_SPSR_FIQ] = val;
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return;
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case MODE_IRQ:
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miscRegs[MISCREG_SPSR_IRQ] = val;
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return;
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case MODE_SVC:
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miscRegs[MISCREG_SPSR_SVC] = val;
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return;
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case MODE_MON:
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miscRegs[MISCREG_SPSR_MON] = val;
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return;
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case MODE_ABORT:
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miscRegs[MISCREG_SPSR_ABT] = val;
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return;
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case MODE_UNDEFINED:
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miscRegs[MISCREG_SPSR_UND] = val;
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return;
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default:
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miscRegs[MISCREG_SPSR] = val;
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return;
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}
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}
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2009-07-10 05:28:27 +02:00
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miscRegs[misc_reg] = val;
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}
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2009-07-09 08:02:20 +02:00
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2009-07-10 05:28:27 +02:00
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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2010-06-02 19:58:09 +02:00
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MiscReg newVal = val;
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2009-11-08 09:07:49 +01:00
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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2010-06-02 19:57:59 +02:00
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CPSR cpsr = val;
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2010-06-02 19:58:13 +02:00
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DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
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cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
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2010-06-02 19:57:59 +02:00
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Addr npc = tc->readNextPC() & ~PcModeMask;
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if (cpsr.j)
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npc = npc | (ULL(1) << PcJBitShift);
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if (cpsr.t)
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npc = npc | (ULL(1) << PcTBitShift);
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tc->setNextPC(npc);
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2009-11-08 09:07:49 +01:00
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}
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2010-06-02 19:58:08 +02:00
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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}
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2010-06-02 19:58:09 +02:00
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switch (misc_reg) {
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case MISCREG_CPACR:
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2010-06-02 19:58:11 +02:00
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
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panic("Disabling coprocessors isn't implemented.\n");
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}
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newVal = newCpacr;
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2010-06-02 19:58:09 +02:00
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}
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break;
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2010-06-02 19:58:09 +02:00
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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break;
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2010-06-02 19:58:13 +02:00
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case MISCREG_TLBTR:
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return;
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2010-06-02 19:58:09 +02:00
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}
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return setMiscRegNoEffect(misc_reg, newVal);
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2009-07-10 05:28:27 +02:00
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}
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2009-07-09 08:02:20 +02:00
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int
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flattenIntIndex(int reg)
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{
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2009-11-08 09:07:49 +01:00
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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2009-11-09 00:49:03 +01:00
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} else if (reg < NUM_INTREGS) {
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return reg;
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2009-11-08 09:07:49 +01:00
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} else {
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2010-06-02 19:58:11 +02:00
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int mode = reg / intRegsPerMode;
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reg = reg % intRegsPerMode;
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switch (mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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return INTREG_USR(reg);
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case MODE_FIQ:
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return INTREG_FIQ(reg);
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case MODE_IRQ:
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return INTREG_IRQ(reg);
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case MODE_SVC:
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return INTREG_SVC(reg);
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case MODE_MON:
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return INTREG_MON(reg);
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case MODE_ABORT:
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return INTREG_ABT(reg);
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case MODE_UNDEFINED:
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return INTREG_UND(reg);
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default:
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panic("Flattening into an unknown mode.\n");
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}
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2009-11-08 09:07:49 +01:00
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}
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2009-07-09 08:02:20 +02:00
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}
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int
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flattenFloatIndex(int reg)
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{
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return reg;
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}
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2009-10-17 10:13:41 +02:00
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void serialize(EventManager *em, std::ostream &os)
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2009-07-10 05:28:27 +02:00
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{}
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2009-10-17 10:13:41 +02:00
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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2009-07-10 05:28:27 +02:00
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{}
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2009-07-09 08:02:20 +02:00
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ISA()
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{
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clear();
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}
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};
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}
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#endif
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