gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini

[root]
type=Root
children=system
eventq_index=0
full_system=true
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000

[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_lpae=true
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]

[system.bridge]
type=Bridge
clk_domain=system.clk_domain
default_p_state=UNDEFINED
delay=50000
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[0]

[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
eventq_index=0
image=system.cf0.image

[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
eventq_index=0
image_file=
read_only=false
table_size=65536

[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
read_only=true

[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.cpu0]
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=16
LSQCheckLoads=true
LSQDepCheckShift=0
SQEntries=16
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=2
decodeWidth=3
default_p_state=UNDEFINED
dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu0.dstage2_mmu
dtb=system.cpu0.dtb
eventq_index=0
fetchBufferSize=16
fetchQueueSize=32
fetchToDecodeDelay=3
fetchTrapLatency=1
fetchWidth=3
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu0.istage2_mmu
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=32
numPhysCCRegs=640
numPhysFloatRegs=192
numPhysIntRegs=128
numROBEntries=40
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=1
renameToROBDelay=1
renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side

[system.cpu0.branchPred]
type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
numThreads=1
useIndirect=true

[system.cpu0.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
writeback_clean=true
cpu_side=system.cpu0.dcache_port
mem_side=system.cpu0.toL2Bus.slave[1]

[system.cpu0.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.dtb

[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker

[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system

[system.cpu0.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.dtb.walker

[system.cpu0.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
port=system.cpu0.toL2Bus.slave[3]

[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
eventq_index=0

[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=2
eventq_index=0
opList=system.cpu0.fuPool.FUList0.opList

[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true

[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1 opList2
count=1
eventq_index=0
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2

[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=12
pipelined=false

[system.cpu0.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu0.fuPool.FUList2.opList

[system.cpu0.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true

[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu0.fuPool.FUList3.opList

[system.cpu0.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true

[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
count=2
eventq_index=0
opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25

[system.cpu0.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=4
pipelined=true

[system.cpu0.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=4
pipelined=true

[system.cpu0.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=4
pipelined=true

[system.cpu0.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=4
pipelined=true

[system.cpu0.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=9
pipelined=true

[system.cpu0.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=3
pipelined=true

[system.cpu0.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true

[system.cpu0.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=9
pipelined=true

[system.cpu0.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList21]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=5
pipelined=true

[system.cpu0.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=9
pipelined=false

[system.cpu0.fuPool.FUList4.opList24]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=33
pipelined=false

[system.cpu0.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true

[system.cpu0.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
writeback_clean=true
cpu_side=system.cpu0.icache_port
mem_side=system.cpu0.toL2Bus.slave[0]

[system.cpu0.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu0.interrupts]
type=ArmInterrupts
eventq_index=0

[system.cpu0.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system

[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.itb

[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker

[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system

[system.cpu0.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu0.itb.walker

[system.cpu0.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
port=system.cpu0.toL2Bus.slave[2]

[system.cpu0.l2cache]
type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
response_latency=12
sequential_access=false
size=1048576
system=system
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
writeback_clean=false
cpu_side=system.cpu0.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[0]

[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
degree=8
eventq_index=0
latency=1
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true

[system.cpu0.l2cache.tags]
type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576

[system.cpu0.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port

[system.cpu0.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system

[system.cpu0.tracer]
type=ExeTracer
eventq_index=0

[system.cpu1]
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=16
LSQCheckLoads=true
LSQDepCheckShift=0
SQEntries=16
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=2
decodeWidth=3
default_p_state=UNDEFINED
dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu1.dstage2_mmu
dtb=system.cpu1.dtb
eventq_index=0
fetchBufferSize=16
fetchQueueSize=32
fetchToDecodeDelay=3
fetchTrapLatency=1
fetchWidth=3
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=32
numPhysCCRegs=640
numPhysFloatRegs=192
numPhysIntRegs=128
numROBEntries=40
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=1
renameToROBDelay=1
renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
wbWidth=8
workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side

[system.cpu1.branchPred]
type=BiModeBP
BTBEntries=2048
BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
numThreads=1
useIndirect=true

[system.cpu1.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
writeback_clean=true
cpu_side=system.cpu1.dcache_port
mem_side=system.cpu1.toL2Bus.slave[1]

[system.cpu1.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.dtb

[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker

[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system

[system.cpu1.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.dtb.walker

[system.cpu1.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
port=system.cpu1.toL2Bus.slave[3]

[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
eventq_index=0

[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=2
eventq_index=0
opList=system.cpu1.fuPool.FUList0.opList

[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true

[system.cpu1.fuPool.FUList1]
type=FUDesc
children=opList0 opList1 opList2
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2

[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=12
pipelined=false

[system.cpu1.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList2.opList

[system.cpu1.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true

[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList3.opList

[system.cpu1.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true

[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
count=2
eventq_index=0
opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25

[system.cpu1.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=4
pipelined=true

[system.cpu1.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=4
pipelined=true

[system.cpu1.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=4
pipelined=true

[system.cpu1.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=4
pipelined=true

[system.cpu1.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=9
pipelined=true

[system.cpu1.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=3
pipelined=true

[system.cpu1.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true

[system.cpu1.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=9
pipelined=true

[system.cpu1.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList21]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=5
pipelined=true

[system.cpu1.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=9
pipelined=false

[system.cpu1.fuPool.FUList4.opList24]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=33
pipelined=false

[system.cpu1.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true

[system.cpu1.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=1
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
writeback_clean=true
cpu_side=system.cpu1.icache_port
mem_side=system.cpu1.toL2Bus.slave[0]

[system.cpu1.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu1.interrupts]
type=ArmInterrupts
eventq_index=0

[system.cpu1.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system

[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.itb

[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker

[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system

[system.cpu1.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
walker=system.cpu1.itb.walker

[system.cpu1.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
port=system.cpu1.toL2Bus.slave[2]

[system.cpu1.l2cache]
type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
response_latency=12
sequential_access=false
size=1048576
system=system
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
writeback_clean=false
cpu_side=system.cpu1.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[1]

[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
degree=8
eventq_index=0
latency=1
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true

[system.cpu1.l2cache.tags]
type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576

[system.cpu1.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port

[system.cpu1.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system

[system.cpu1.tracer]
type=ExeTracer
eventq_index=0

[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000

[system.intrctrl]
type=IntrControl
eventq_index=0
sys=system

[system.iobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
response_latency=2
use_default_range=false
width=16
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma

[system.iocache]
type=Cache
children=tags
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=50
sequential_access=false
size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]

[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024

[system.l2c]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]

[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304

[system.membus]
type=CoherentXBar
children=badaddr_responder snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side

[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=0
pio_latency=100000
pio_size=8
power_model=Null
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default

[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system

[system.physmem]
type=DRAMCtrl
IDD0=0.075000
IDD02=0.000000
IDD2N=0.050000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.000000
IDD2P12=0.000000
IDD3N=0.057000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.000000
IDD3P12=0.000000
IDD4R=0.187000
IDD4R2=0.000000
IDD4W=0.165000
IDD4W2=0.000000
IDD5=0.220000
IDD52=0.000000
IDD6=0.000000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=0
tXPDLL=0
tXS=0
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[5]

[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
system=system

[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470024192
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[18]

[system.realview.cf_ctrl]
type=IdeController
BAR0=471465984
BAR0LegacyIO=true
BAR0Size=256
BAR1=471466240
BAR1LegacyIO=true
BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
default_p_state=UNDEFINED
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
power_model=Null
system=system
dma=system.iobus.slave[2]
pio=system.iobus.master[9]

[system.realview.clcd]
type=Pl111
amba_id=1315089
clk_domain=system.clk_domain
default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=46
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=471793664
pio_latency=10000
pixel_clock=41667
power_model=Null
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[5]

[system.realview.dcc]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null

[system.realview.dcc.osc_cpu]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.dcc.osc_ddr]
type=RealViewOsc
dcc=0
device=8
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.dcc.osc_hsbm]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.dcc.osc_pxl]
type=RealViewOsc
dcc=0
device=5
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.dcc.osc_smb]
type=RealViewOsc
dcc=0
device=6
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.dcc.osc_sys]
type=RealViewOsc
dcc=0
device=7
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain

[system.realview.energy_ctrl]
type=EnergyCtrl
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dvfs_handler=system.dvfs_handler
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470286336
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[22]

[system.realview.ethernet]
type=IGbE
BAR0=0
BAR0LegacyIO=false
BAR0Size=131072
BAR1=0
BAR1LegacyIO=false
BAR1Size=0
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=4213
ExpansionROM=0
HeaderType=0
InterruptLine=1
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=255
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=0
SubClassCode=0
SubsystemID=4104
SubsystemVendorID=32902
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
default_p_state=UNDEFINED
eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
power_model=Null
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
system=system
tx_desc_cache_size=64
tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
dma=system.iobus.slave[4]
pio=system.iobus.master[24]

[system.realview.generic_timer]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_phys=29
int_virt=27
system=system

[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
cpu_addr=738205696
cpu_pio_delay=10000
default_p_state=UNDEFINED
dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
gem5_extensions=true
int_latency=10000
it_lines=128
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
platform=system.realview
power_model=Null
system=system
pio=system.membus.master[2]

[system.realview.hdlcd]
type=HDLcd
amba_id=1314816
clk_domain=system.clk_domain
default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=117
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=721420288
pio_latency=10000
pixel_buffer_size=2048
pixel_chunk=32
power_model=Null
pxl_clk=system.realview.dcc.osc_pxl
system=system
vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[6]

[system.realview.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=2
InterruptPin=2
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
default_p_state=UNDEFINED
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
power_model=Null
system=system
dma=system.iobus.slave[3]
pio=system.iobus.master[23]

[system.realview.kmi0]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=44
is_mouse=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470155264
pio_latency=100000
power_model=Null
system=system
vnc=system.vncserver
pio=system.iobus.master[7]

[system.realview.kmi1]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=45
is_mouse=true
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470220800
pio_latency=100000
power_model=Null
system=system
vnc=system.vncserver
pio=system.iobus.master[8]

[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=739246080
pio_latency=100000
pio_size=4095
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[12]

[system.realview.lan_fake]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=436207616
pio_latency=100000
pio_size=65535
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[19]

[system.realview.local_cpu_timer]
type=CpuLocalTimer
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=738721792
pio_latency=100000
power_model=Null
system=system
pio=system.membus.master[4]

[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null

[system.realview.mcc.osc_clcd]
type=RealViewOsc
dcc=0
device=1
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain

[system.realview.mcc.osc_mcc]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain

[system.realview.mcc.osc_peripheral]
type=RealViewOsc
dcc=0
device=2
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain

[system.realview.mcc.osc_system_bus]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain

[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system

[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470089728
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[21]

[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:67108863
port=system.membus.master[1]

[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
power_model=Null
system=system
pio=system.iobus.master[2]

[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
idreg=35979264
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=469827584
pio_latency=100000
power_model=Null
proc_id0=335544320
proc_id1=335544320
system=system
pio=system.iobus.master[1]

[system.realview.rtc]
type=PL031
amba_id=3412017
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=100000
int_num=36
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=471269376
pio_latency=100000
power_model=Null
system=system
time=Thu Jan  1 00:00:00 2009
pio=system.iobus.master[10]

[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=true
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=469893120
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[16]

[system.realview.timer0]
type=Sp804
amba_id=1316868
clk_domain=system.clk_domain
clock0=1000000
clock1=1000000
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num0=34
int_num1=34
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470876160
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[3]

[system.realview.timer1]
type=Sp804
amba_id=1316868
clk_domain=system.clk_domain
clock0=1000000
clock1=1000000
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num0=35
int_num1=35
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470941696
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[4]

[system.realview.uart]
type=Pl011
clk_domain=system.clk_domain
default_p_state=UNDEFINED
end_on_eot=false
eventq_index=0
gic=system.realview.gic
int_delay=100000
int_num=37
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470351872
pio_latency=100000
platform=system.realview
power_model=Null
system=system
terminal=system.terminal
pio=system.iobus.master[0]

[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470417408
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[13]

[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470482944
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[14]

[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470548480
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[15]

[system.realview.usb_fake]
type=IsaFake
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=452984832
pio_latency=100000
pio_size=131071
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[20]

[system.realview.vgic]
type=VGic
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
hv_addr=738213888
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_delay=10000
platform=system.realview
power_model=Null
ppint=25
system=system
vcpu_addr=738222080
pio=system.membus.master[3]

[system.realview.vram]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=402653184:436207615
port=system.iobus.master[11]

[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470745088
pio_latency=100000
power_model=Null
system=system
pio=system.iobus.master[17]

[system.terminal]
type=Terminal
eventq_index=0
intr_control=system.intrctrl
number=0
output=true
port=3456

[system.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side

[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system

[system.vncserver]
type=VncServer
eventq_index=0
frame_capture=false
number=0
port=5900

[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000