gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                1524580                       # Simulator instruction rate (inst/s)
host_mem_usage                                 213492                       # Number of bytes of host memory used
host_seconds                                    57.94                       # Real time elapsed on the host
host_tick_rate                             2332726052                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    88340673                       # Number of instructions simulated
sim_seconds                                  0.135169                       # Number of seconds simulated
sim_ticks                                135168766000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     2301488000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency   2119190000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              14463584                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency    8388371000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.010250                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              149793                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency   7938992000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.010250                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         149793                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 50768.948371                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                34679456                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     10689859000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.006035                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                210559                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  10058182000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.006035                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           210559                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50768.948371                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               34679456                       # number of overall hits
system.cpu.dcache.overall_miss_latency    10689859000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.006035                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               210559                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  10058182000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.006035                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          210559                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 200248                       # number of replacements
system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4078.872537                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle              947635000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   147714                       # number of writebacks
system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_hits                     34890015                       # DTB hits
system.cpu.dtb.data_misses                      97400                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                     20276638                       # DTB read hits
system.cpu.dtb.read_misses                      90148                       # DTB read misses
system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                    14613377                       # DTB write hits
system.cpu.dtb.write_misses                      7252                       # DTB write misses
system.cpu.icache.ReadReq_accesses           88438074                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 18810.691297                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               88361638                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency     1437814000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000864                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                76436                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency   1208506000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000864                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           76436                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                1156.021220                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            88438074                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 18810.691297                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297                       # average overall mshr miss latency
system.cpu.icache.demand_hits                88361638                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency      1437814000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000864                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 76436                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency   1208506000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000864                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            76436                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 18810.691297                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               88361638                       # number of overall hits
system.cpu.icache.overall_miss_latency     1437814000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000864                       # miss rate for overall accesses
system.cpu.icache.overall_misses                76436                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency   1208506000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000864                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           76436                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  74391                       # number of replacements
system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1871.768668                       # Cycle average of tags in use
system.cpu.icache.total_refs                 88361638                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses                88442008                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                    88438074                       # ITB hits
system.cpu.itb.fetch_misses                      3934                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency   7466056000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            143578                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   5743120000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       143578                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            137202                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                 93905                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    2251444000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.315571                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               43297                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1731880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.315571                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          43297                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses           6215                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency    321256000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses             6215                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency    248600000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses         6215                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses          147714                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              147714                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.630830                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             280780                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                  93905                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     9717500000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.665557                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               186875                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   7475000000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.665557                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          186875                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                 93905                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    9717500000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.665557                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              186875                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   7475000000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.665557                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         186875                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                147561                       # number of replacements
system.cpu.l2cache.sampled_refs                172766                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             18255.825674                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  108986                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                  120634                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                        270337532                       # number of cpu cycles simulated
system.cpu.num_insts                         88340673                       # Number of instructions executed
system.cpu.num_refs                          35321418                       # Number of memory references
system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls

---------- End Simulation Statistics   ----------