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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini

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x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[root]
type=Root
children=system
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
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full_system=true
stats: updates due to changes to ticksToCycles()
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sim_quantum=0
x86: regressions: add switcher full test
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxX86System
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
acpi_description_table_pointer=system.acpi_description_table_pointer
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
x86: regressions: add switcher full test
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e820_table=system.e820_table
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
x86: regressions: add switcher full test
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load_addr_mask=18446744073709551615
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
readfile=tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
[system.acpi_description_table_pointer]
type=X86ACPIRSDP
children=xsdt
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
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oem_id=
revision=2
rsdt=Null
xsdt=system.acpi_description_table_pointer.xsdt
[system.acpi_description_table_pointer.xsdt]
type=X86ACPIXSDT
creator_id=
creator_revision=0
entries=
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
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oem_id=
oem_revision=0
oem_table_id=
[system.apicbridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
x86: regressions: add switcher full test
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delay=50000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
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ranges=11529215046068469760:11529215046068473855
req_size=16
resp_size=16
master=system.membus.slave[0]
slave=system.iobus.master[0]
[system.bridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
delay=50000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0]
type=AtomicSimpleCPU
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simpoint_interval=100000000
simpoint_profile=false
simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0.dcache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
addr_ranges=0:18446744073709551615
assoc=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=32768
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.dcache.tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0.dtb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
port=system.toL2Bus.slave[3]
[system.cpu0.icache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
addr_ranges=0:18446744073709551615
assoc=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=32768
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.icache.tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0.interrupts]
type=X86LocalApic
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu0.apic_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[3]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
int_slave=system.membus.master[2]
pio=system.membus.master[1]
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0.isa]
type=X86ISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu0.itb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
port=system.toL2Bus.slave[2]
[system.cpu0.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu1]
type=TimingSimpleCPU
children=dtb isa itb tracer
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
function_trace=false
function_trace_start=0
interrupts=Null
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
switched_out=true
system=system
tracer=system.cpu1.tracer
workload=
[system.cpu1.dtb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
[system.cpu1.isa]
type=X86ISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu1.itb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
[system.cpu1.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu2]
type=DerivO3CPU
children=branchPred dtb fuPool isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
fetchBufferSize=64
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=Null
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=true
numIQEntries=64
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
numPhysCCRegs=1280
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=true
system=system
tracer=system.cpu2.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=
[system.cpu2.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu2.dtb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu2.dtb.walker
[system.cpu2.dtb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
[system.cpu2.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu2.fuPool.FUList0]
type=FUDesc
children=opList
count=6
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList0.opList
[system.cpu2.fuPool.FUList0.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu2.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
[system.cpu2.fuPool.FUList1.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=IntMult
opLat=3
[system.cpu2.fuPool.FUList1.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu2.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
[system.cpu2.fuPool.FUList2.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu2.fuPool.FUList2.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu2.fuPool.FUList2.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu2.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
[system.cpu2.fuPool.FUList3.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu2.fuPool.FUList3.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu2.fuPool.FUList3.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu2.fuPool.FUList4]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList4.opList
[system.cpu2.fuPool.FUList4.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu2.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
[system.cpu2.fuPool.FUList5.opList00]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList01]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList02]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList03]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList04]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList05]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList06]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu2.fuPool.FUList5.opList07]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList08]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu2.fuPool.FUList5.opList09]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList10]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu2.fuPool.FUList5.opList11]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList12]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList13]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList14]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList15]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu2.fuPool.FUList5.opList16]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList17]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu2.fuPool.FUList5.opList18]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList19]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu2.fuPool.FUList6]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList6.opList
[system.cpu2.fuPool.FUList6.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu2.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
[system.cpu2.fuPool.FUList7.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu2.fuPool.FUList7.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu2.fuPool.FUList8]
type=FUDesc
children=opList
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
opList=system.cpu2.fuPool.FUList8.opList
[system.cpu2.fuPool.FUList8.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu2.isa]
type=X86ISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.cpu2.itb]
type=X86TLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=64
walker=system.cpu2.itb.walker
[system.cpu2.itb.walker]
type=X86PagetableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
num_squash_per_cycle=4
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system=system
[system.cpu2.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.e820_table]
type=X86E820Table
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
children=entries0 entries1 entries2 entries3
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.e820_table.entries0]
type=X86E820Entry
addr=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
range_type=1
size=654336
[system.e820_table.entries1]
type=X86E820Entry
addr=654336
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
range_type=2
size=394240
[system.e820_table.entries2]
type=X86E820Entry
addr=1048576
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
range_type=1
size=133169152
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
[system.e820_table.entries3]
type=X86E820Entry
addr=4294901760
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
range_type=2
size=65536
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
imcr_present=true
spec_rev=4
[system.intel_mp_table]
type=X86IntelMPConfigTable
children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
ext_entries=system.intel_mp_table.ext_entries
local_apic=4276092928
oem_id=
oem_table_addr=0
oem_table_size=0
product_id=
spec_rev=4
[system.intel_mp_table.base_entries00]
type=X86IntelMPProcessor
bootstrap=true
enable=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
family=0
feature_flags=0
local_apic_id=0
local_apic_version=20
model=0
stepping=0
[system.intel_mp_table.base_entries01]
type=X86IntelMPIOAPIC
address=4273995776
enable=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
id=1
version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
bus_type=ISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
bus_type=PCI
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.intel_mp_table.base_entries04]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=16
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=16
trigger=ConformTrigger
[system.intel_mp_table.base_entries05]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=0
trigger=ConformTrigger
[system.intel_mp_table.base_entries06]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=0
trigger=ConformTrigger
[system.intel_mp_table.base_entries07]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=1
trigger=ConformTrigger
[system.intel_mp_table.base_entries08]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=1
trigger=ConformTrigger
[system.intel_mp_table.base_entries09]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=3
trigger=ConformTrigger
[system.intel_mp_table.base_entries10]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=3
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=3
trigger=ConformTrigger
[system.intel_mp_table.base_entries11]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=4
trigger=ConformTrigger
[system.intel_mp_table.base_entries12]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=4
trigger=ConformTrigger
[system.intel_mp_table.base_entries13]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=5
trigger=ConformTrigger
[system.intel_mp_table.base_entries14]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=5
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=5
trigger=ConformTrigger
[system.intel_mp_table.base_entries15]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=6
trigger=ConformTrigger
[system.intel_mp_table.base_entries16]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=6
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=6
trigger=ConformTrigger
[system.intel_mp_table.base_entries17]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=7
trigger=ConformTrigger
[system.intel_mp_table.base_entries18]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=7
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=7
trigger=ConformTrigger
[system.intel_mp_table.base_entries19]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=8
trigger=ConformTrigger
[system.intel_mp_table.base_entries20]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=8
trigger=ConformTrigger
[system.intel_mp_table.base_entries21]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=9
trigger=ConformTrigger
[system.intel_mp_table.base_entries22]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=9
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=9
trigger=ConformTrigger
[system.intel_mp_table.base_entries23]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=10
trigger=ConformTrigger
[system.intel_mp_table.base_entries24]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=10
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=10
trigger=ConformTrigger
[system.intel_mp_table.base_entries25]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=11
trigger=ConformTrigger
[system.intel_mp_table.base_entries26]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=11
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=11
trigger=ConformTrigger
[system.intel_mp_table.base_entries27]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=12
trigger=ConformTrigger
[system.intel_mp_table.base_entries28]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=12
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=12
trigger=ConformTrigger
[system.intel_mp_table.base_entries29]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=13
trigger=ConformTrigger
[system.intel_mp_table.base_entries30]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=13
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=13
trigger=ConformTrigger
[system.intel_mp_table.base_entries31]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.base_entries32]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=1
dest_io_apic_intin=14
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
bus_id=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
parent_bus=1
subtractive_decode=true
[system.intrctrl]
type=IntrControl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sys=system
[system.iobus]
type=NoncoherentBus
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
header_cycles=1
use_default_range=true
width=8
default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
[system.iocache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
addr_ranges=0:134217727
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
forward_snoops=false
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=1024
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.iocache.tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[18]
mem_side=system.membus.slave[4]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.l2c]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
addr_ranges=0:18446744073709551615
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
size=4194304
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.l2c.tags
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=4194304
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.membus]
type=CoherentBus
children=badaddr_responder
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
header_cycles=1
system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default
[system.pc]
type=Pc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
intrctrl=system.intrctrl
system=system
[system.pc.behind_pci]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854779128
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[12]
[system.pc.com_1]
type=Uart8250
children=terminal
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
pio_addr=9223372036854776824
pio_latency=100000
platform=system.pc
system=system
terminal=system.pc.com_1.terminal
pio=system.iobus.master[13]
[system.pc.com_1.terminal]
type=Terminal
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.pc.fake_com_2]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854776568
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[14]
[system.pc.fake_com_3]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854776808
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[15]
[system.pc.fake_com_4]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854776552
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[16]
[system.pc.fake_floppy]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854776818
pio_latency=100000
pio_size=2
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[17]
[system.pc.i_dont_exist]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
fake_mem=false
pio_addr=9223372036854775936
pio_latency=100000
pio_size=1
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[11]
[system.pc.pciconfig]
type=PciConfigAll
bus=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio_addr=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
pio_latency=30000
platform=system.pc
size=16777216
system=system
pio=system.iobus.default
[system.pc.south_bridge]
type=SouthBridge
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
pic2=system.pc.south_bridge.pic2
pit=system.pc.south_bridge.pit
platform=system.pc
speaker=system.pc.south_bridge.speaker
[system.pc.south_bridge.cmos]
type=Cmos
children=int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=100000
system=system
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.master[1]
[system.pc.south_bridge.cmos.int_pin]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.dma1]
type=I8237
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
pio_addr=9223372036854775808
pio_latency=100000
system=system
pio=system.iobus.master[2]
[system.pc.south_bridge.ide]
type=IdeController
children=disks0 disks1
BAR0=496
BAR0LegacyIO=true
BAR0Size=8
BAR1=1012
BAR1LegacyIO=true
BAR1Size=3
BAR2=368
BAR2LegacyIO=true
BAR2Size=8
BAR3=884
BAR3LegacyIO=true
BAR3Size=3
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
CapabilityPtr=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
MaximumLatency=0
MinimumGrant=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
ProgIF=128
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
config_latency=20000
ctrl_offset=0
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
io_shift=0
pci_bus=0
pci_dev=4
pci_func=0
pio_latency=30000
platform=system.pc
system=system
config=system.iobus.master[4]
dma=system.iobus.slave[1]
pio=system.iobus.master[3]
[system.pc.south_bridge.ide.disks0]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
image=system.pc.south_bridge.ide.disks0.image
[system.pc.south_bridge.ide.disks0.image]
type=CowDiskImage
children=child
child=system.pc.south_bridge.ide.disks0.image.child
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
image_file=
read_only=false
table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
image_file=/dist/disks/linux-x86.img
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
read_only=true
[system.pc.south_bridge.ide.disks1]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
image=system.pc.south_bridge.ide.disks1.image
[system.pc.south_bridge.ide.disks1.image]
type=CowDiskImage
children=child
child=system.pc.south_bridge.ide.disks1.image.child
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
image_file=
read_only=false
table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
image_file=/dist/disks/linux-bigswap2.img
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines0.sink
source=system.pc.south_bridge.pic1.output
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=0
[system.pc.south_bridge.int_lines1]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines1.sink
source=system.pc.south_bridge.pic2.output
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=2
[system.pc.south_bridge.int_lines2]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines2.sink
source=system.pc.south_bridge.cmos.int_pin
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=0
[system.pc.south_bridge.int_lines3]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines3.sink
source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=0
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines4.sink
source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=2
[system.pc.south_bridge.int_lines5]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines5.sink
source=system.pc.south_bridge.keyboard.keyboard_int_pin
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=1
[system.pc.south_bridge.int_lines6]
type=X86IntLine
children=sink
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sink=system.pc.south_bridge.int_lines6.sink
source=system.pc.south_bridge.keyboard.mouse_int_pin
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
number=12
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
external_int_pic=system.pc.south_bridge.pic1
int_latency=1000
pio_addr=4273995776
pio_latency=100000
system=system
int_master=system.iobus.slave[2]
pio=system.iobus.master[10]
[system.pc.south_bridge.keyboard]
type=I8042
children=keyboard_int_pin mouse_int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
command_port=9223372036854775908
data_port=9223372036854775904
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=100000
system=system
pio=system.iobus.master[5]
[system.pc.south_bridge.keyboard.keyboard_int_pin]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.keyboard.mouse_int_pin]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.pic1]
type=I8259
children=output
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
mode=I8259Master
output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=100000
slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.master[6]
[system.pc.south_bridge.pic1.output]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.pic2]
type=I8259
children=output
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
mode=I8259Slave
output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=100000
slave=Null
system=system
pio=system.iobus.master[7]
[system.pc.south_bridge.pic2.output]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.pit]
type=I8254
children=int_pin
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=100000
system=system
pio=system.iobus.master[8]
[system.pc.south_bridge.pit.int_pin]
type=X86IntSourcePin
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.pc.south_bridge.speaker]
type=PcSpeaker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905
pio_latency=100000
system=system
pio=system.iobus.master[9]
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=RaBaChCo
banks_per_rank=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
burst_length=8
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
channels=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
in_addr_map=true
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
static_backend_latency=10000
static_frontend_latency=10000
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tBURST=5000
tCL=13750
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRAS=35000
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRRD=6250
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
tWTR=7500
tXAW=40000
write_buffer_size=32
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
write_high_thresh_perc=70
write_low_thresh_perc=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
port=system.membus.master[3]
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
[system.smbios_table]
type=X86SMBiosSMBiosTable
children=structures
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
major_version=2
minor_version=5
structures=system.smbios_table.structures
[system.smbios_table.structures]
type=X86SMBiosBiosInformation
characteristic_ext_bytes=
characteristics=
emb_cont_firmware_major=0
emb_cont_firmware_minor=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
major=0
minor=0
release_date=06/08/2008
rom_size=0
starting_addr_segment=0
vendor=
version=
[system.toL2Bus]
type=CoherentBus
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
header_cycles=1
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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