2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.506533 # Number of seconds simulated
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sim_ticks 506532922500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 123802 # Simulator instruction rate (inst/s)
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host_tick_rate 36394183 # Simulator tick rate (ticks/s)
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host_mem_usage 263680 # Number of bytes of host memory used
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host_seconds 13917.96 # Real time elapsed on the host
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sim_insts 1723073849 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 1013065846 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 315530681 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 258143608 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 18340117 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 278231679 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 251492518 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 20187042 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 3509 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 313870814 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2260978275 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 315530681 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 271679560 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 505214363 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 101212316 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 104532477 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 328 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 301063999 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 6471754 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1002877503 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.508485 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.026652 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 497663194 49.62% 49.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 37228948 3.71% 53.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 66606984 6.64% 59.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 71463437 7.13% 67.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 48876391 4.87% 71.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 60858176 6.07% 78.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 55641741 5.55% 83.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 19086125 1.90% 85.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 145452507 14.50% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 1002877503 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.311461 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.231818 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 341996878 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 89611613 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 478932686 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 13077462 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 79258864 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 48434993 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 667 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2450495134 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2272 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 79258864 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 363548311 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 45530514 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 19331 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 469125778 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 45394705 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2388695520 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 19323 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 2689291 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 36489292 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2366306887 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 11027767520 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 11027765811 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1709 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 659986931 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 807 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 800 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 96182774 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 645482909 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 225885161 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 74160075 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 61434686 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2258262830 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 791 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2062701357 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 3805579 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 528742156 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1247770653 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 334 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1002877503 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.056783 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.854473 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 290604713 28.98% 28.98% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 157949600 15.75% 44.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 174074952 17.36% 62.08% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 138718897 13.83% 75.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 127592193 12.72% 88.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 68569400 6.84% 95.48% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 32608818 3.25% 98.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10494958 1.05% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 2263972 0.23% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 1002877503 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 2048519 7.53% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 180 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 19993289 73.47% 81.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 5169269 19.00% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1260792748 61.12% 61.12% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1057290 0.05% 61.17% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 606172338 29.39% 90.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 194678965 9.44% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2062701357 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.036098 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 27211257 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.013192 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5159296764 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2790611549 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1986898801 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 289 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 125 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2089912468 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 146 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 50578054 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 159556137 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 214192 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 3609503 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 51038115 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 451763 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 79258864 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 21822492 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1097447 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2258327486 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 7242198 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 645482909 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 225885161 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 728 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 222856 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 63033 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 3609503 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 18937238 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1831687 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 20768925 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2019710082 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 582582512 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 42991275 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 63865 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 773812500 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 240248597 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 191229988 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.993661 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1997612417 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1986898926 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1306276482 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2072612086 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.961273 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.630256 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 535450016 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 18340062 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 923618640 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.865569 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.641231 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 417808285 45.24% 45.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 197293052 21.36% 66.60% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 87052087 9.43% 76.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 38036803 4.12% 80.14% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 20677754 2.24% 82.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 32036200 3.47% 85.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 19042329 2.06% 87.91% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 12956798 1.40% 89.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 98715332 10.69% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 923618640 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 1723073867 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 660773817 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 485926771 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 213462365 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 98715332 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 3083426592 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4596573652 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 890932 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 10188343 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.587941 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.587941 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.700851 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.700851 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 10108398592 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1972581504 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 113 # number of floating regfile reads
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.misc_regfile_reads 3008512623 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 11 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 611.156574 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 301062972 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 404111.371812 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 611.156574 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.298416 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 301062972 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 301062972 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 301062972 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1027 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1027 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1027 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 35502000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 35502000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 35502000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 301063999 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 301063999 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 301063999 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34568.646543 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34568.646543 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34568.646543 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 282 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 745 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 745 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 25601000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 25601000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 25601000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.758389 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 9572249 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.950948 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 684182956 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 9576345 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 71.445103 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 3569933000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4087.950948 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.998035 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 516770094 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 167412740 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 684182834 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 684182834 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 10495679 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 5173307 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_misses 15668986 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 15668986 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 184475737500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 128174581168 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 312650318668 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 312650318668 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 527265773 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 699851820 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 699851820 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.019906 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.029975 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.022389 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.022389 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 17576.350944 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 24776.140517 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 19953.449360 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 19953.449360 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 267517156 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 91155 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2934.750217 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 17208.333333 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 3128719 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 2812049 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 3280592 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 6092641 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 6092641 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 7683630 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1892715 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 9576345 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 9576345 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 91948284500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 45274333885 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 137222618385 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 137222618385 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014573 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.013683 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.013683 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11966.776706 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23920.312295 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 2927741 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26823.943722 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7852858 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2955065 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.657423 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 103629166500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 16019.902231 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 10804.041491 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.488889 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.329713 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 5656678 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 3128719 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 980284 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 6636962 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 6636962 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2027695 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 912433 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2940128 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2940128 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 69610117500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31648090500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 101258208000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 101258208000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 7684373 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 3128719 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1892717 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 9577090 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 9577090 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.263873 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.306996 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.306996 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34329.678527 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.385667 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34440.067915 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34440.067915 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 56477000 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 6600 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8557.121212 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.writebacks 1217526 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2027684 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912433 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2940117 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2940117 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 63223600000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815061500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 92038661500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 92038661500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263871 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.306995 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.306995 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31180.203621 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31580.468374 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
