2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.524442 # Number of seconds simulated
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sim_ticks 524441606000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 101251 # Simulator instruction rate (inst/s)
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host_tick_rate 30817067 # Simulator tick rate (ticks/s)
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host_mem_usage 257952 # Number of bytes of host memory used
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host_seconds 17017.90 # Real time elapsed on the host
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sim_insts 1723073904 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 1048883213 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 317450426 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 259852467 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 18436703 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 279904663 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 254677721 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 20220648 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 4428 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 315501768 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2280935015 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 317450426 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 274898369 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 509081814 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 103935328 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 124227879 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 270 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 303015456 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 6379891 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1031116877 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.459992 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.013809 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::0 522035116 50.63% 50.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 37818104 3.67% 54.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 65533745 6.36% 60.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 69512456 6.74% 67.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 53414736 5.18% 72.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 61047606 5.92% 78.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 57075579 5.54% 84.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 19670108 1.91% 85.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 145009427 14.06% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::total 1031116877 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.302656 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.174632 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 346461175 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 106173290 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 477865699 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 18312225 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 82304488 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 48528259 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2473135818 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2289 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 82304488 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 368931509 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 50902781 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 20077 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 472181274 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 56776748 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2411760057 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 18939 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 5901279 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 44092765 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2386823429 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 11134835710 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 11134834246 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1464 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1706320039 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 680503385 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 855 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 848 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 119214990 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 651763451 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 230362141 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 123114303 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 108844207 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2285934828 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 851 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2067906375 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 3040241 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 557691684 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1352307582 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 383 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1031116877 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.005501 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.810247 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 302093175 29.30% 29.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 161453829 15.66% 44.96% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 185974655 18.04% 62.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 152722281 14.81% 77.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 122859599 11.92% 89.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 63855935 6.19% 95.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 30343304 2.94% 98.85% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10954294 1.06% 99.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 859805 0.08% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::total 1031116877 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 735734 3.76% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 145 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 17865428 91.35% 95.11% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 956298 4.89% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1267972738 61.32% 61.32% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1165735 0.06% 61.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 9 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 605808033 29.30% 90.67% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 192959848 9.33% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2067906375 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.971532 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 19557605 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.009458 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5189527225 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2846700346 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1993811028 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 105 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2087463854 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 48700640 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 165836668 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 182984 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 3082033 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 55515084 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 451401 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 82304488 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 22549936 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1320929 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2286019853 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 6521602 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 651763451 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 230362141 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 777 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 333118 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 65136 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 3082033 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 18892989 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1847041 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 20740030 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2026288483 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 583345448 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 41617892 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_nop 84174 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 773137523 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 241378100 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 189792075 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.931853 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2004592772 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1993811133 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1313765556 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2094642495 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.900890 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.627203 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1723073922 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 563083903 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 468 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 18443845 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 948812390 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.816032 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.570732 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 421119309 44.38% 44.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 219659546 23.15% 67.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 84920332 8.95% 76.49% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 40130029 4.23% 80.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 24924955 2.63% 83.34% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 30334777 3.20% 86.54% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 23612661 2.49% 89.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 12752294 1.34% 90.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 91358487 9.63% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 948812390 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 1723073922 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.refs 660773839 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 485926782 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branches 213462376 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 1536941897 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 91358487 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 3143611129 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4654874733 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 997575 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 17766336 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1723073904 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1723073904 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.608728 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.608728 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.642770 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.642770 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 10134733413 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1980533280 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 92 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 35 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 3028358925 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 148 # number of misc regfile writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.replacements 9 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.tagsinuse 611.010403 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 303014437 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 739 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 410033.067659 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 611.010403 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.298345 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 303014437 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 303014437 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 303014437 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1019 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 35224000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 35224000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 35224000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 303015456 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 303015456 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 303015456 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34567.222767 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34567.222767 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34567.222767 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 739 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 739 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 739 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 25462500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 25462500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 25462500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34455.345061 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.replacements 9572098 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4088.159469 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 687277052 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 9576194 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 71.769333 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 3603059000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4088.159469 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.998086 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 519599165 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 167677732 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 82 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 73 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 687276897 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 687276897 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 10430920 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 4908315 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_misses 15339235 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 15339235 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 181621482000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 122280886057 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 303902368057 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 303902368057 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 530030085 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 85 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 73 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 702616132 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 702616132 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.019680 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.028440 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.035294 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.021832 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.021832 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 17411.837307 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 24913.007021 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 19812.094153 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 19812.094153 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 267003640 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 90682 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2944.395139 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 21777.777778 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 3128448 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 2747497 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 3015544 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 5763041 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 5763041 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 7683423 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1892771 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 9576194 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 9576194 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 90753159500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 45245223293 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 135998382793 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 135998382793 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014496 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.013629 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.013629 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11811.553197 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23904.224702 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.replacements 2927988 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26803.816569 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7852126 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2955312 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.656953 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 105427800500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 15979.704689 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 10824.111881 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.487662 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.330326 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 5656220 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 3128448 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 980310 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 6636530 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 6636530 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2027940 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 912463 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2940403 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2940403 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 69613457000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31659273500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 101272730500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 101272730500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 7684160 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 3128448 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1892773 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 9576933 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 9576933 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.263912 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482077 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.307030 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.307030 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34327.177826 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.501118 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34441.785871 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34441.785871 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 56425500 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 6606 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8541.553134 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 1217599 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2027928 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912463 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2940391 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2940391 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 63193895000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28814819500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 92008714500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 92008714500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263910 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482077 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307028 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307028 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.804068 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.164854 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
