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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
sim_seconds 1.171613 # Number of seconds simulated
sim_ticks 1171612619000 # Number of ticks simulated
final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
host_inst_rate 639669 # Simulator instruction rate (inst/s)
host_op_rate 818158 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12399663305 # Simulator tick rate (ticks/s)
host_mem_usage 384708 # Number of bytes of host memory used
host_seconds 94.49 # Real time elapsed on the host
sim_insts 60440687 # Number of instructions simulated
sim_ops 77305655 # Number of ops (including micro ops) simulated
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory
system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 69306 # number of replacements
system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use
system.l2c.total_refs 1685686 # Total number of references to valid blocks.
system.l2c.sampled_refs 134505 # Sample count of references to valid blocks.
system.l2c.avg_refs 12.532516 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.occ_percent::cpu1.inst 0.041973 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.031343 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.803513 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 4104 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1844 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 401511 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 204865 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5725 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 448415 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 143316 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1211742 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 616867 # number of Writeback hits
system.l2c.Writeback_hits::total 616867 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1168 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1743 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56775 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 52975 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 109750 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4104 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1844 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 401511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 261640 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5725 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 448415 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 196291 # number of demand (read+write) hits
system.l2c.demand_hits::total 1321492 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4104 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1844 # number of overall hits
system.l2c.overall_hits::cpu0.inst 401511 # number of overall hits
system.l2c.overall_hits::cpu0.data 261640 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5725 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits
system.l2c.overall_hits::cpu1.inst 448415 # number of overall hits
system.l2c.overall_hits::cpu1.data 196291 # number of overall hits
system.l2c.overall_hits::total 1321492 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_misses::cpu0.inst 5773 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 7865 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_misses::cpu1.inst 5025 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses
system.l2c.ReadReq_misses::total 22316 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 4668 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3562 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 8230 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 67164 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 72393 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139557 # number of ReadExReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_misses::cpu0.inst 5773 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 75029 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_misses::cpu1.inst 5025 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 76039 # number of demand (read+write) misses
system.l2c.demand_misses::total 161873 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_misses::cpu0.inst 5773 # number of overall misses
system.l2c.overall_misses::cpu0.data 75029 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_misses::cpu1.inst 5025 # number of overall misses
system.l2c.overall_misses::cpu1.data 76039 # number of overall misses
system.l2c.overall_misses::total 161873 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 300844500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 409319998 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 262047000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 190080500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1162656498 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 28957997 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 27214000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 56171997 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3588000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6004000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 9592000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3493801976 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3769288495 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7263090471 # number of ReadExReq miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_miss_latency::cpu0.inst 300844500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3903121974 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 262047000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3959368995 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8425746969 # number of demand (read+write) miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_miss_latency::cpu0.inst 300844500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3903121974 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 262047000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3959368995 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8425746969 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4105 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1846 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 407284 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 212730 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5729 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 453440 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 146962 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1234058 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 616867 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 616867 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5836 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4137 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 9973 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 774 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 580 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1354 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 123939 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 125368 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 249307 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 4105 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1846 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 407284 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 336669 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 5729 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1962 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 453440 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 272330 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1483365 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 4105 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1846 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 407284 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 336669 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 5729 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1962 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 453440 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 272330 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1483365 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001083 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014174 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036972 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011082 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024809 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.018083 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.799863 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861010 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.825228 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728682 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825862 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.770310 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.541912 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.577444 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.559780 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001083 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014174 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.222857 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.279216 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.109126 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014174 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.222857 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011082 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.279216 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.109126 # miss rate for overall accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52112.333276 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52043.229243 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52148.656716 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52133.982447 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52099.681753 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6203.512639 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7640.089837 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 6825.273026 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6361.702128 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12534.446764 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 9196.548418 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52018.968138 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52067.029892 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52043.899417 # average ReadExReq miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52051.589635 # average overall miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52051.589635 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.writebacks::writebacks 64180 # number of writebacks
system.l2c.writebacks::total 64180 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 5772 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 7865 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 5025 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3646 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 22315 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4668 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3562 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 8230 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 67164 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 72393 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 139557 # number of ReadExReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 5772 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 75029 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 5025 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 76039 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 161872 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 5772 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 75029 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 5025 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 76039 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 161872 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 231552000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314935000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 201743000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 146326000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 894836000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186889000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 142710000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 329599000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22593000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19208000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 41801000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2687800500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2900558000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5588358500 # number of ReadExReq MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 231552000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3002735500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 201743000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3046884000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6483194500 # number of demand (read+write) MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 231552000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3002735500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 201743000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3046884000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6483194500 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9312662000 # number of ReadReq MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122159781000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131741924000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694882000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30588601000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31283483000 # number of WriteReq MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10007544000 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152748382000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 163025407000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036972 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024809 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.018083 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799863 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861010 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.825228 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728682 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770310 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541912 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577444 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.559780 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.read_hits 7077919 # DTB read hits
system.cpu0.dtb.read_misses 3740 # DTB read misses
system.cpu0.dtb.write_hits 5661726 # DTB write hits
system.cpu0.dtb.write_misses 804 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.read_accesses 7081659 # DTB read accesses
system.cpu0.dtb.write_accesses 5662530 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.hits 12739645 # DTB hits
system.cpu0.dtb.misses 4544 # DTB misses
system.cpu0.dtb.accesses 12744189 # DTB accesses
system.cpu0.itb.inst_hits 29451654 # ITB inst hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.itb.inst_misses 2205 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses
system.cpu0.itb.hits 29451654 # DTB hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.itb.misses 2205 # DTB misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.itb.accesses 29453859 # DTB accesses
system.cpu0.numCycles 2343225238 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.committedInsts 28759206 # Number of instructions committed
system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.num_func_calls 1242118 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls
system.cpu0.num_int_insts 33058293 # number of integer instructions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.num_fp_insts 3860 # number of float instructions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.num_mem_refs 13408219 # number of memory refs
system.cpu0.num_load_insts 7415624 # Number of load instructions
system.cpu0.num_store_insts 5992595 # Number of store instructions
system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles
system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles
system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed
system.cpu0.icache.replacements 408292 # number of replacements
system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use
system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits
system.cpu0.icache.overall_hits::total 29042833 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses
system.cpu0.icache.overall_misses::total 408804 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.writebacks::writebacks 20827 # number of writebacks
system.cpu0.icache.writebacks::total 20827 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408804 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 408804 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 408804 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 408804 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 408804 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 408804 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4872150503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4872150503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4872150503 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4872150503 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4872150503 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4872150503 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.replacements 330880 # number of replacements
system.cpu0.dcache.tagsinuse 457.764906 # Cycle average of tags in use
system.cpu0.dcache.total_refs 12284019 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 331392 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 37.067941 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 457.764906 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.894072 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.894072 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6607497 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6607497 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5356507 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5356507 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147994 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 147994 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149732 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 149732 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11964004 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11964004 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11964004 # number of overall hits
system.cpu0.dcache.overall_hits::total 11964004 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 228069 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 228069 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 141727 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 141727 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9289 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9289 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7498 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7498 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 369796 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 369796 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 369796 # number of overall misses
system.cpu0.dcache.overall_misses::total 369796 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3436407000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3436407000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917296000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 4917296000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100570500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 100570500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74480000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 74480000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8353703000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 8353703000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8353703000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 8353703000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6835566 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6835566 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5498234 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5498234 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157283 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 157283 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157230 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 157230 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12333800 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12333800 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12333800 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12333800 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033365 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.033365 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025777 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.025777 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059059 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059059 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047688 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047688 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029982 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029982 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029982 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029982 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks
system.cpu0.dcache.writebacks::total 306522 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.read_hits 8311872 # DTB read hits
system.cpu1.dtb.read_misses 3663 # DTB read misses
system.cpu1.dtb.write_hits 5828412 # DTB write hits
system.cpu1.dtb.write_misses 1436 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.read_accesses 8315535 # DTB read accesses
system.cpu1.dtb.write_accesses 5829848 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.hits 14140284 # DTB hits
system.cpu1.dtb.misses 5099 # DTB misses
system.cpu1.dtb.accesses 14145383 # DTB accesses
system.cpu1.itb.inst_hits 32285286 # ITB inst hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.itb.inst_misses 2171 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses
system.cpu1.itb.hits 32285286 # DTB hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.itb.misses 2171 # DTB misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.itb.accesses 32287457 # DTB accesses
system.cpu1.numCycles 2341739150 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.committedInsts 31681481 # Number of instructions committed
system.cpu1.committedOps 40192806 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 36864445 # Number of integer alu accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.num_func_calls 962202 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls
system.cpu1.num_int_insts 36864445 # number of integer instructions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.num_fp_insts 6793 # number of float instructions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read
system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.num_mem_refs 14678127 # number of memory refs
system.cpu1.num_load_insts 8633777 # Number of load instructions
system.cpu1.num_store_insts 6044350 # Number of store instructions
system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles
system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles
system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.kern.inst.quiesce 43917 # number of quiesce instructions executed
system.cpu1.icache.replacements 454429 # number of replacements
system.cpu1.icache.tagsinuse 478.358537 # Cycle average of tags in use
system.cpu1.icache.total_refs 31830341 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 454941 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 69.965866 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 92993102000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 478.358537 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.934294 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.934294 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 31830341 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 31830341 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 31830341 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 31830341 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 31830341 # number of overall hits
system.cpu1.icache.overall_hits::total 31830341 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 454941 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 454941 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 454941 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 454941 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 454941 # number of overall misses
system.cpu1.icache.overall_misses::total 454941 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6716097000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6716097000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6716097000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6716097000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6716097000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6716097000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32285282 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 32285282 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 32285282 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 32285282 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 32285282 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 32285282 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014091 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014091 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014091 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014091 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014091 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014091 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14762.567014 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14762.567014 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.icache.writebacks::writebacks 23436 # number of writebacks
system.cpu1.icache.writebacks::total 23436 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454941 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 454941 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 454941 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 454941 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 454941 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 454941 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5350372502 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5350372502 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5350372502 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5350372502 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5350372502 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5350372502 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014091 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.014091 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.014091 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dcache.replacements 292285 # number of replacements
system.cpu1.dcache.tagsinuse 472.233445 # Cycle average of tags in use
system.cpu1.dcache.total_refs 11962904 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 292625 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 40.881346 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 84136899000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 472.233445 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.922331 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.922331 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 6947233 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 6947233 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4827936 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4827936 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81814 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 81814 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82788 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 82788 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 11775169 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11775169 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11775169 # number of overall hits
system.cpu1.dcache.overall_hits::total 11775169 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 170612 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 170612 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 150091 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 150091 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11098 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11098 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10047 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10047 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 320703 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 320703 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 320703 # number of overall misses
system.cpu1.dcache.overall_misses::total 320703 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2368289000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2368289000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5141096000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 5141096000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106270500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 106270500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87322000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 87322000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 7509385000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7509385000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 7509385000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7509385000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117845 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7117845 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978027 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4978027 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92912 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 92912 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92835 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 92835 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 12095872 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 12095872 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 12095872 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 12095872 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023970 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.023970 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030151 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030151 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119446 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119446 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108224 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108224 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9575.644260 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9575.644260 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8691.350652 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8691.350652 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dcache.writebacks::writebacks 266082 # number of writebacks
system.cpu1.dcache.writebacks::total 266082 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170612 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 170612 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150091 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 150091 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11098 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11098 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10038 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10038 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 320703 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 320703 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 320703 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 320703 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855824122 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855824122 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4690597670 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4690597670 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72957002 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72957002 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57198010 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57198010 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6546421792 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink